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//可直接透過synthesis tool用於PLD,FPGA不可 LUT delay則要採其他方式。
/ F. z2 [/ M6 t) ^( R6 E7 C//所有註解都要保留( Y2 k$ A6 h) r" ?0 ?, K0 S
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`timescale 1 ns / 1 ns* v& X w& E. ?$ |: `1 {
module xclk(sclk,ena,set,outp);
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6 X" l# E" r6 Oinput sclk,ena;, c8 [, a- e7 v0 U
input [1:0]set;9 Y$ B* D% H; [, l7 R$ }. ~
output outp;
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wire outp;6 f9 H3 i) a- h& K5 ~
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; b# B) V: s9 d% M, V/**** Node preservation for nodeA **************/
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1 {, d. @& H% j) O3 T//exemplar attribute nodeA_5 preserve_signal true( K" H: t. _( Z# J0 j2 O4 w9 e
( E- R3 |& L1 J) p! ~6 A8 c//exemplar attribute nodeA_4 opt keep
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/**** The following comment form also works ****/
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//exemplar attribute nodeA_3 preserve_signal true
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/ h3 _% q0 c: k6 q//exemplar attribute nodeA_3 opt keep2 E( M: L; C8 l: y# w3 G2 G
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/**** The following comment form also works ****/
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( u9 T4 n/ n1 ]# e//exemplar attribute nodeA_2 preserve_signal true; N; x5 j+ T' p, O6 Q. D
' t. i3 \& U2 E# k7 |' N: ]7 _' D//exemplar attribute nodeA_2 opt keep
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6 ?$ @7 p% p# R" U4 ]/**** The following comment form also works ****/3 n$ o4 U: T; z# H8 D* m
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//exemplar attribute nodeA_1 preserve_signal true
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. L* g, b2 c! `: ~6 t! r//exemplar attribute nodeA_1 opt keep
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/**** The following comment form also works ****/
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/*exemplar attribute nodeA_0 preserve_signal true
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) Q, Z% R/ |0 z! {+ A9 Sexemplar attribute nodeA_0 opt keep*/ ) V# L9 h. {. X( e$ i) u
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wire nodeA/* synthesis syn_keep=1 opt="keep"*/;
+ p3 o! b5 e- o$ y, X; X/ zwire nodeA_0/* synthesis syn_keep=1 opt="keep"*/;
X( D3 J, J8 j8 a- `9 Dwire nodeA_1/* synthesis syn_keep=1 opt="keep"*/;
( [9 i& s+ l3 n5 B+ s- U4 Xwire nodeA_2/* synthesis syn_keep=1 opt="keep"*/;
\8 ]# p' | A1 Z Vwire nodeA_3/* synthesis syn_keep=1 opt="keep"*/;
9 ]0 n6 D* |1 Zwire nodeA_4/* synthesis syn_keep=1 opt="keep"*/;
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assign#1 nodeA_0 = sclk & ena;1 @$ l6 Y4 s* s6 d$ H% }- T. `5 M+ o
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assign#1 nodeA_1 = ~ nodeA_0;
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assign#1 nodeA_3 = ~ nodeA_2;
. D2 z5 r4 V. J: c: ~$ y. o/ f. zassign#1 nodeA_4 = ~ nodeA_3;! Z M* i- u! D4 S& J L
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reg xout;8 n) i& O# n; O5 E9 u$ z
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always@(nodeA_1,nodeA_2,nodeA_3,nodeA_4,set)
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. G0 S+ Q7 t0 x0 {& q; U7 v: ~ 1: xout =#1 nodeA_2;
% w2 l- ^* J) e) w! Z 2: xout =#1 nodeA_3;" U1 q& B) ]% H8 z3 k3 b4 F! ]) B
3: xout =#1 nodeA_4;9 R V) g" \* [& F
default: xout =#1 nodeA_1;# k; H$ K3 o' j3 T0 T
endcase4 N9 u2 F: g9 b; R
4 {' \% R" Y& {' p& r- Vassign#1 nodeA = xout;
Y0 E: q7 C* n8 _assign#1 outp = ena ? nodeA^sclk : 1'bz;1 C# J: N% e! j6 y1 w v
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endmodule+ G+ @9 L/ a2 _$ V. j o7 j3 I* ~
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`timescale 1 ns / 1 ns
1 ~( B, y! ~, B! pmodule xclk_tf();: K5 ?2 c7 `- f0 h; e( }' h1 ~
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reg sclk;
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( Z9 s/ k0 q, X0 W& s3 L+ l reg [1:0] set;
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% _- ^" A4 X' m# G. Y/ Z// Outputs3 u) Y0 ?1 O1 D7 Z, `3 r: ]
wire outp;0 X0 l; z* h. T) V. o; v
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xclk UUT (
# G4 B! W) S6 X& j8 d .sclk(sclk),
9 H0 f/ C+ n% n! u% {/ F; t, E .ena(ena), O, y/ _( L- b! `: F. c
.set(set), 4 S9 ~1 c) w- f# _( `$ y
.outp(outp)
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initial begin7 K3 a2 z Z r
sclk = 0;
0 J2 h4 U* k$ O" p9 @/ S ena = 0;
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always# 5 sclk = !sclk;
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M8 o4 Z2 n3 \' Hinitial begin+ n* e5 |0 K- ?' h
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ena = 1;) Z& ]# T! R: |* G/ E- E' d% {
#2000
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set = 3;
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end* d Q1 X/ ^% W/ F
endmodule // xclk_tf |
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