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DIP Application Engineer
+ O1 s6 h! U( n7 l/ G# x) @公 司:One world top EDA company
# i7 ?0 q! G: P/ O, s, K工作地点:上海) t8 L0 y6 t7 h: _. d
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Responsibilities:
$ [1 s5 b: ?7 s9 @3 S4 k/ H+ T' P2 e! V1) Providing direct technical support to customers in presale stage to persuade customers to adopt Cadence Design IP solutions for their applications6 w0 _0 b$ z' {1 F" ^4 y
2) Interface with customer architects and Design IP business unit to enable evaluation of application specific IP performance and features per customer’s SOC requirements.
5 B8 B' ?& @* |9 h1 N' w! u2) Working with the sales team to manage the IP activities in the region to achieve a high customer satisfaction rate and for building strong customer relationships
: b7 e8 s4 y6 ?. x* y0 I: Y3) Providing customer feedback on new/existing requirements for Design IP usage from customers to the IP business unit.
; \, j8 p; F' c4) Providing direct technical customer support and assistance to enable customers to successfully integrate/use Design IP in their SOC.
- ~/ y( j3 K, E! {, e5) Writing application notes in situation to facilitate customer usage of the IP
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t& Z& g! s$ d$ y7 W3 S ZPosition Requirements : , n' v* \& F% i6 O2 c3 s" V' L% t$ ?" L
1) Experience in digital/analog design and implementation of controllers/phy ' q' }+ }8 V) F9 M( Z
2) Knowledge of serdes and backend implementation is a plus 2 R, \ Z6 p/ j/ t) N8 C
3) Experience with SOC architecture include on-chip fabric (AMBA/Sonics OCP/Arteris NOC), external interconnect protocols (e.g PCIe/Ethernet) and DRAM memory protocols (DDRn, LPDDRn), DRAM PHYs, .NAND Flash (Async, ONFI, Toggle NAND), eMMC/SD, MIPI. L1 L; o. T, b5 x0 r7 d2 d
4) Knowing serdes/analog IP is a plus
7 V/ Z4 v0 \: p6 y) D, l/ A5) Exposure to IP-based SOC design flow and real tape-out experience. % J$ l' s" j( Z5 T0 r
6) Good written and verbal communication skills and problem solving skills are required.
+ u% H( \# I4 l' c: ]$ @. v7) Ability to conduct technical meetings, presentations, seminars and training to customers and to the sales team+ r( p$ e. j; m' ^+ z$ H
8) Travel within AP region may be required. * V% f; g+ b9 d, _
9) Good understanding of the semiconductor IP marketplace and ecosystem is a plus. |
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