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Senior Physical Design Engineer+ d) |+ Y3 @. y1 E# c
公 司:A famous IC company# Y6 G+ f1 L' O# ^
工作地点:南京
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Key Responsibilities
9 P9 F: T9 J$ }+ |Depending on experience, key responsibilities will involve some of the following: # o* \6 }$ q, @! e0 }( {7 K
IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification. 9 q, k3 [8 o* x9 u5 h* S
As a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
2 H% K6 J) z- E. e) LLeading a team of physical design engineers and resolving the technical related issues.
) K$ S8 W$ ?$ V. F7 q) tCrosstalk analysis, power analysis, and static timing analysis. ! p5 {6 o% k7 i% Q% N6 R
Write scripts in Tcl to improve productivity. 7 ]2 N9 }. ?& c% C5 m
) F) W' K x, B6 D$ l/ TExperience: 5+ years in physical implementation engineering
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- I" I) ]7 A% z) ?! eEssential skills / E7 c/ U8 B, u
MS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills
4 |7 v4 g c0 J2 R; {+ V8 \Experience with Magma or Synopsys place-and-route tool set and physical design project implementation. ( j+ o5 d* `$ \% W; X
Good programming skill. Capable of writing Tcl or Perl.
9 V) F4 e+ Y6 m+ l! JFamiliar with synthesis, static timing analysis. $ k' c8 x' N" Z- E% d
Self-motivated team worker, good verbal and written communication skills in English. 3 Q! y, W2 k( ~. e) ^) z; u+ m
Technical and team leadership proffered. Previous management experience highly desired. " v3 ]0 e% G, ?' D8 Q
Experience with synthesis, DFT, and verification is preferred. |
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