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招聘公司:A famous IC company
4 d5 B" `1 i0 m- X招聘岗位:ASIC CAD Engineer0 ~4 R3 }# G2 u* U4 K2 Z) @
工作地点:Shanghai
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岗位描述Description of the Role / Responsibilities:
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- H, t! M% n9 |1 X* Z( O2 Z! vParticipate in the design and implementation of the leading edge ASIC chip.4 a3 A% o1 H' _% [& P+ j
Your focus is on design flow ' D- @7 o: d- X) T; h: g% Q, }+ d
Ensure the design methodology correct and improve automation and productivity. The main flow steps include:
3 B+ ?& n9 Z% t0 t7 ~+ ` TFE: Synthesis, Simulation, STA, Design Check and memory compiler etc.
) T# l/ R9 L9 Y& ?: IBE: Place and Routing, Physical verification, Signal integrity, Power analysis etc.
; F8 {2 J$ \; F7 {4 GAnother important part of the job is doing support to FE /BE team. % M/ v/ t% h, N% `$ E1 I4 i ^
When they have a real design issue and can’t solved by themselves, you may be asked to jump in for debug and find a solution. Usually you will work with EDA vendors on such case. 8 k* r7 E% ?. u* |; x8 J4 H9 _
Responsibilities besides support project work also include interfacing with other implementation experts across different development locations, and driving the continuous improvement of advanced implementation methods to Trident digital TV and Set-Top-Box projects teams.
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9 C! p% ], D" l2 o职位要求Experience and Skills Required:
0 `9 s% c& Q# S, X+ `( y( JEssential
6 F0 k6 q% b, p/ _) E. b! IMajor in Electronic Engineering or Computer Science. - f( g9 ?& A9 t, ~- z* R' e4 o
Master (or Bachelor 2+ years related experience) 6 L( y/ \" S& P# u6 F
Strong programming skill with one or more following items( Perl,Tcl, C/C++ etc).& T0 W) @1 z) O$ E( p+ Q
Experience with industry standard development EDA tools and flow.
x! h. L1 s) N: H& PFE engineer: DC, RTL Compiler, PT, Conformal LEC, NC. VCS
5 [6 x7 S: g( W7 w1 pBE engineer: SOC encounter, Apache Redhawk etc.
! A) l; u8 g8 ~/ m# {5 U, X/ U$ @Good written and fluent oral English.
, W2 b2 R! n, J1 F6 `# u0 HGood communication skills and team work. & f& |/ s" L# h) e# S
( f% u6 J6 g% Z$ [% s2 YDesirable
2 \! h+ m3 y1 R3 }4 GReal ASIC project experience as a FE or BE designer is a plus. |
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