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本帖最後由 masonchung 於 2010-1-21 09:23 AM 編輯
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C2 CC1200高清编解码芯片
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CC1200 Family
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: H1 I/ i4 p0 V; c; lCC1200 is C2 Microsystems’ second generation media processor family for Full HD video applications. It is based on the innovative Jazz 2 architecture, which is optimized for next-generation high-definition broadcast services and broadband rich media applications. CC1200 decodes all current broadcast formats and a wide variety of Internet content formats and performs high quality audio post-processing and video de-interlacing and scaling for high-definition display. CC1200 transcodes content into several formats for place-shifting and for side-loading onto portable devices. CC1200 encodes video for video monitoring, video chat and place shifting applications. CC1200 has a dual-core Symmetric Multiprocessor (SMP) which, with hardware acceleration of graphics operations, delivers very high applications processing performance.
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* D, K+ p' d1 P6 N' CFeatures
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High applications and media processing performance - h. q- G, _ f, F t' X* \
7 R- K5 `% z Y8 V, ]. X9 SDual Core SMP 4-way superscalar RISC architecture @ 350 MHz * e+ z& F Q0 K3 D c" A( W% g2 Q e
Dual hardware threads per core 2 w: s" m8 Y7 c& x
256-bit SIMD Vector Unit
# X# N; _/ J2 }" y8 z; xCodec Acceleration Processors for digital broadcast standards ; i- h/ {1 Z$ D' F5 S1 i
Motion estimation, entropy engines , \6 V0 A. g6 }1 ~
2D Graphics Accelerator with DirectFB, OpenVG 1.1 support 7 M5 Z/ U( d) G! V# j* `. ?
Display Processor
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Extensive rich media codec support % z% a; Q6 a, D- |. q2 Q- o6 T2 k
* Y# S" _2 X% I& T3 Z" bH.264, MPEG-2/4, VC-1, FLV, RM
( ]; k6 U q0 KDecoding of digital broadcast standards up to Full HD 1 q, ^3 b1 g5 U% b8 }
Decoding of internet content standards up to 720p
4 }1 a# | d! \Encoding at D1 resolution and above
1 g! _2 Q; m9 N9 w% ]High level of device integration 1 t7 \ q9 W. w* E: W4 T) I4 \7 E; Q
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DRAM Memory: 64-/32-bit DDR2 @ 400MHz, 128-512 MB
% O1 S+ j1 Z h3 w4 J! b% k9 R; cParallel NAND Flash
. M. E& q+ S3 q7 kEthernet 10/100/1000M MAC with RMII/RGMII interface
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PCI-Express: Ethernet/WiFi
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MPEG-2 transport stream 8 R' F7 i* i+ b$ {
Digital A/V – HDMI, BT-656/BT-1120, SPDIF, I2S
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Package: 27mm x 27 mm, Pb-Free
6 C# L% I: ?! s E9 W9 PCC1200 Block Diagram: a2 A5 I5 {) h8 c8 p
7 k, Y% G0 Q5 x5 y A* T# Y( y- TSupported Standards: ]4 O" @7 I" b1 u( Z: t
The Jazz media processor architecture permits the encoding and decoding of a wide range of video and audio compression standards
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