|
本帖最後由 masonchung 於 2010-1-21 09:23 AM 編輯 ) X2 T# b6 \& L- K! i0 P0 y
1 v ~) f5 A$ F) ~) {% @3 x( T) @C2 CC1200高清编解码芯片
% ^: E% |1 o$ @- y4 n3 YCC1200 Media Processor Famiy
; D% e( g* H/ Y, E% E8 Z7 q" P3 w8 } }) m) x
1 X1 d5 w( v5 c3 U
9 s( Q; g0 k$ s5 C& i4 @ E
5 e* [" R0 s9 e# m1 S
% A6 i6 I2 c: E* OCC1200 Family$ k) @4 E1 J3 Z; s; ?; r
0 K' p; ~8 X8 w% ECC1200 is C2 Microsystems’ second generation media processor family for Full HD video applications. It is based on the innovative Jazz 2 architecture, which is optimized for next-generation high-definition broadcast services and broadband rich media applications. CC1200 decodes all current broadcast formats and a wide variety of Internet content formats and performs high quality audio post-processing and video de-interlacing and scaling for high-definition display. CC1200 transcodes content into several formats for place-shifting and for side-loading onto portable devices. CC1200 encodes video for video monitoring, video chat and place shifting applications. CC1200 has a dual-core Symmetric Multiprocessor (SMP) which, with hardware acceleration of graphics operations, delivers very high applications processing performance.
5 I o- z3 d/ R& i* `2 v3 j- Z
# p* ^! `' b- pFeatures
& q+ D4 h* a1 @* _# a0 u5 s- b
" o. E' {$ L P: }High applications and media processing performance
( Y% b# z5 @ ^; ^, {7 e9 m: g, A* D, |4 E
Dual Core SMP 4-way superscalar RISC architecture @ 350 MHz
, h9 P! d9 n7 g3 P) rDual hardware threads per core
+ x# G9 N0 R0 e256-bit SIMD Vector Unit
* \* ], V/ w; V9 m dCodec Acceleration Processors for digital broadcast standards
/ J" E3 M* h/ H+ C) z( sMotion estimation, entropy engines ) E$ Z; h3 }' v6 f7 K" A
2D Graphics Accelerator with DirectFB, OpenVG 1.1 support
5 q5 L# Z+ a. ^Display Processor
$ k5 Q( C' c1 e, W eSecurity Processor # m4 Q& c8 W* L3 U" Y
Extensive rich media codec support
1 S& D; t4 |2 z( [$ h& H' ~4 n5 e- }8 |/ n! W. p; ?
H.264, MPEG-2/4, VC-1, FLV, RM 6 K6 g- r) ]. @
Decoding of digital broadcast standards up to Full HD % }: `5 ~7 I- w
Decoding of internet content standards up to 720p
: Y5 Y4 V8 A& o9 ?! s5 jEncoding at D1 resolution and above ( q. Y" y' n+ Z6 y4 j
High level of device integration 6 \$ ^5 N# a' b( G1 \! Q" a$ y6 M0 U
# X) Z. ]+ o4 X$ f# W
DRAM Memory: 64-/32-bit DDR2 @ 400MHz, 128-512 MB 2 q/ {+ f, l6 V: H1 p
Parallel NAND Flash 7 V: Y' h5 o0 J; t( |
Ethernet 10/100/1000M MAC with RMII/RGMII interface V' Q! i; ]" C) X8 d: W
USB2.0 OTG
# L' V0 |" r' {0 q& ^PCI-Express: Ethernet/WiFi . B% c ^# h! u9 g3 x
SDIO
2 }2 S/ h, p( g0 r* b y& @MPEG-2 transport stream 9 r" ~& s3 P( I s8 p3 c9 i4 R/ P
Digital A/V – HDMI, BT-656/BT-1120, SPDIF, I2S
9 ^& [' l$ u) l" y2 g& l( M; \Analog Video Out – YPbPr, CVBS . w0 ?: b0 p9 w7 D7 P7 M
Package: 27mm x 27 mm, Pb-Free
5 n% R3 N- y. Z3 V9 Z9 g% lCC1200 Block Diagram
5 S3 Y* Q( q5 b; }" S8 [5 b5 l" N) C, z7 {1 M3 L0 G% u' k3 Z
Supported Standards
' V2 l4 P; F( j; UThe Jazz media processor architecture permits the encoding and decoding of a wide range of video and audio compression standards
2 \) F$ ?! `# u8 h& _! s |
本帖子中包含更多資源
您需要 登錄 才可以下載或查看,沒有帳號?申請會員
x
|