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本帖最後由 masonchung 於 2010-1-21 09:23 AM 編輯
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C2 CC1200高清编解码芯片
% W1 y* F$ A+ J! }6 h7 V+ K" q' NCC1200 Media Processor Famiy: H$ H6 x' R/ Q n) {$ ]% o; S; q
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; W: j2 p) G0 ]% g h M8 eCC1200 Family( T5 d5 h# w6 c/ U
5 |3 H/ z0 z$ Q) B d1 G, |# }CC1200 is C2 Microsystems’ second generation media processor family for Full HD video applications. It is based on the innovative Jazz 2 architecture, which is optimized for next-generation high-definition broadcast services and broadband rich media applications. CC1200 decodes all current broadcast formats and a wide variety of Internet content formats and performs high quality audio post-processing and video de-interlacing and scaling for high-definition display. CC1200 transcodes content into several formats for place-shifting and for side-loading onto portable devices. CC1200 encodes video for video monitoring, video chat and place shifting applications. CC1200 has a dual-core Symmetric Multiprocessor (SMP) which, with hardware acceleration of graphics operations, delivers very high applications processing performance. + C! l- ^* Q, A. g& [9 Q( ]) V
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Features9 a7 w t6 m+ n9 X' {/ f
# H3 ^3 ?4 H2 ?; FHigh applications and media processing performance $ K9 H+ m$ o: |- L) f: @& W
J2 V2 T3 y' I9 h2 rDual Core SMP 4-way superscalar RISC architecture @ 350 MHz 2 r/ Z1 T( K" J) ?$ R
Dual hardware threads per core
- P' M: e- i5 l256-bit SIMD Vector Unit
# S1 u2 W* R9 n+ R! @2 N7 {2 w5 vCodec Acceleration Processors for digital broadcast standards $ `1 J. A8 T+ {' K+ I. P; n
Motion estimation, entropy engines
1 M3 W; A+ r* R4 ~- q2D Graphics Accelerator with DirectFB, OpenVG 1.1 support
" W! v7 ^; K/ t8 i/ Y+ Q& S) D8 ADisplay Processor - t F& q$ J4 z# g& O/ [
Security Processor / r8 D+ A4 T8 e$ H
Extensive rich media codec support 5 w% W( D: T/ ~ A( p! U
' n$ |/ y# E$ kH.264, MPEG-2/4, VC-1, FLV, RM
1 y+ V+ S! V( K1 _& ^( GDecoding of digital broadcast standards up to Full HD
' m' K+ t: k, j1 @- mDecoding of internet content standards up to 720p % ?( ]" j ~2 k0 d
Encoding at D1 resolution and above & g( A+ Y3 Z: G
High level of device integration
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DRAM Memory: 64-/32-bit DDR2 @ 400MHz, 128-512 MB
1 g5 A$ l3 D1 f$ E0 E7 O2 S/ _Parallel NAND Flash
9 I7 a" b4 H7 h# e; X% [( g' bEthernet 10/100/1000M MAC with RMII/RGMII interface
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. y0 \" n3 ^$ v4 m) s( xPCI-Express: Ethernet/WiFi : `0 i( p) F/ K+ o# |+ A* Z* ?
SDIO / U6 Q" T* p) b6 | r" }: k
MPEG-2 transport stream
) W N1 T2 @( ]! n+ J( u8 NDigital A/V – HDMI, BT-656/BT-1120, SPDIF, I2S 5 Q5 T* e% D" I$ `
Analog Video Out – YPbPr, CVBS ; M; X" l5 p* f
Package: 27mm x 27 mm, Pb-Free
+ ?% z! w3 ^, u" D6 O+ H1 }CC1200 Block Diagram; _% p1 d# f0 F9 E1 I9 U7 u
. h9 c" t/ b$ Z% VSupported Standards
, ?& k; P [% h- w. C. m* ]+ xThe Jazz media processor architecture permits the encoding and decoding of a wide range of video and audio compression standards
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