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In order to save test device, usually will do Power to Ground then IO to Power/Ground and the last is Io to IO. 5 J3 B. ^9 Z# n- t: Y
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The reason is:5 F( v0 y% I$ a; z
1. If power to ground can not pass, the rest combination has less chance to pass
7 D1 v5 q, m9 z3 y. ]: j2. Usually power pin count is less than IO pin count. It is fast to get an idea how the chip's ESD level* e" N2 `+ n* M
3. If failed, it's easy to find the failed ESD zapping combination |
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