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//some example
" Y+ b" [6 P) h/ Q
7 C$ ?% k2 l" ^( B// define variable
0 m6 t' @" g5 E3 O/ qVARIABLE RVM1 0.077 // Metal-1 resistor : Y1 D8 D2 Y. I, z1 E- r* q
VARIABLE RVM2 0.055 // Metal-2 resistor
1 d U8 K# c2 J4 kVARIABLE RVM3 0.055 // Metal-3 resistor
$ M2 j* o% b D( t4 U% ~9 l" Q' x6 M" m3 f' m) u
// lvs option
: d. f' U/ ?& z; `/ jLVS SPICE PREFER PINS YES$ N0 ~5 P# d8 s% |6 s3 p& G; g
LVS ABORT ON SUPPLY ERROR NO4 h0 c7 }7 n& ]: Z% ] y1 _
LVS ALL CAPACITOR PINS SWAPPABLE YES# ?8 h" K. s3 z: s0 ~
LVS RECOGNIZE GATES NONE7 J- i3 U- i# R& J M. H$ `+ |
LVS IGNORE PORTS NO
9 n: H3 j* [; `. Z! ELVS CHECK PORT NAMES YES
& m7 p8 ^2 u; m- F8 M# Z2 dLVS REDUCE PARALLEL BIPOLAR YES
, z$ O; V( C$ @ Q. K/ i* ~LVS REDUCE PARALLEL MOS YES' q) [ d# ^% k' a9 T6 ~9 S
LVS REDUCE PARALLEL DIODES YES
0 T, I. Y0 M5 }LVS REDUCE PARALLEL CAPACITORS YES
) X1 t8 g, J) ?) jLVS REDUCE PARALLEL RESISTORS YES
9 E/ N- ]6 Y+ X6 e, _1 ]& ^LVS REDUCE SERIES RESISTORS YES //Smashes series resistors
. X/ g+ c1 h. i( [ J, ~* TLVS REDUCE SERIES CAPACITORS YES //Smashes series capacitors0 m" s% x& n! L* X! \
LVS REDUCE SPLIT GATES NO //Smashes MOS split-gates.
9 [4 @- t- h+ N- V2 ]//LVS FILTER UNUSED OPTION B D E O2 t7 ]3 b! g( s, Y: N M
LVS FILTER UNUSED OPTION AB RC RE RG
( `+ h, [9 h4 i1 J; JLVS PROPERTY RESOLUTION MAXIMUM 65536 // ALL+ C" {* y$ l6 ?% p* Q
0 {- R9 J. e9 c5 a$ X# A// layer definition
/ \; B# G2 j( GLAYER DNW 1 // DNW -- Deep N-Well
& z4 F1 c0 U0 r% m3 aLAYER NTN 11 // Native Device Blocked Implant
& A5 n6 {! e F( r+ @LAYER NWELL 3 // NW -- N-Well
o0 u: m r2 g& wLAYER OD 8 6 7 // OD -- Thin Oxide/ I+ J3 y& u, h" n# }' r5 b4 j
4 C* {) b, N; W7 ?
// layer operation
, E/ ~: U' R) C7 f+ _+ H6 o2 Qrpolywo1 = POLYG AND RHDMY
" |$ }' k6 v/ e0 ]( b" G5 Rrpolywo2 = rpolywo1 AND RPO 7 @# g/ `7 c4 X6 K! W+ C' ]3 U
diff = OD NOT RODMY 2 D8 w0 C( O- i& y! j! h* P; D
rp1 = RPDMY NOT INTERACT diff + _/ Z) L; d# z5 y9 k
p1rdum = rp1 INTERACT POLYG& t" E7 C R7 ^
. }& ]1 F' h4 H/ D6 z2 U, T9 T
// connect statement
- ~& Q+ R3 I; d D# G# @/ ?6 }CONNECT metal1 c2poly BY pl2co
' V. r' n! |# [* N" _CONNECT metal1 tndiff BY pl1co: j9 O- U: [. w. Q
CONNECT metal1 poly BY pl1co
5 E5 S- |0 s3 uCONNECT metal1 tpdiff BY pl1co
: ~- {0 P) M6 H! yCONNECT metal2 metal1 BY VIA1( c3 t8 c$ `) \, _
CONNECT metal3 metal2 BY VIA2, p1 g/ v: P4 v2 U+ l
CONNECT metal4 metal3 BY VIA3
5 I+ E2 ?* y* D; c5 } mCONNECT metal5 metal4 BY VIA4* d; O |( U9 v+ x2 h" a) U: R( g
CONNECT metal6 metal5 BY VIA5
) s1 U4 ?7 Y* M- ZCONNECT metal7 metal6 BY VIA6
0 C% \ u) M( ?: r. D: sCONNECT metal8 metal7 BY VIA7
7 k# ?' j0 N* I6 s& {1 BCONNECT metal8 CTM_M7 BY CV72 z. t9 J1 y( K# w. j3 d
% m* M: C/ u9 M1 T6 P
// device definition2 r+ Y1 G) R) Y/ y1 F& j
DEVICE MN(nmos) nmos poly(G) ndiff(S) ndiff(D) psub(B) [
8 x, u( ]; Z7 r& y5 J1 ~ property W,L3 ~. Z, c: B' I6 Q4 N1 ?1 P: r
W=(perimeter_coincide(nmos, ndiff ) + perimeter_inside(nmos, ndiff)) / 2
9 Q ?5 l& a+ O' F( A1 R L=area(nmos) / W) m+ B8 l. s' h( w! n
]0 d; J8 _% `! t, A, L
0 h. ]2 n4 V) ]// trace property: {! j! ~' D1 N( o8 z* \3 t5 W5 E* X
TRACE PROPERTY MN(nmos) L L 01 g7 B5 z, E& o& o5 F: }
TRACE PROPERTY MN(nmos) W W 0 |
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