library compiler建DFF cell的疑問

霜淇淋

各位好，小弟打算跑HSPICE改變一下cell library的資料
  R. v) S4 O2 d; j8 f# r但有部分還是不太理解，以下是D-Flip Flop(DFF)接腳D及CLK部分
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& t6 ]  ~3 Y  w( W7 Q4 }( Z  U  pin(D) {
    nextstate_type : data;
    direction : input ;
    capacitance : 0.001165;
    internal_power() {
, a7 b% _) Z; J. N      when : "!CK";
+ {- t& ^5 y9 @% E      power(POWER_7x1) {
        index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
      }
+ F  f0 _- R9 x+ u$ r    }

values值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?
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" N. ^2 {$ l" v) w4 A/ g    internal_power() {
      when : "CK";
) v* @& h3 f; @      power(POWER_7x1) {
        index_1("0.009645,0.016106,0.025991,0.046674,0.088957,0.216628,0.447814");
        values("0.000127,0.000122,0.000120,0.000119,0.000117,0.000116,0.000114");
, Z$ f5 ]! P/ l/ l0 O5 z      }
    }
5 b7 C- O! g7 j, d& B0 z    timing() {
& Y( l) R8 j! g, t! ^! m! ^      related_pin : "CK";
      sdf_edges   : both_edges;
      timing_type : setup_rising;
      rise_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("0.029659,0.026470,0.036963",\
               "0.032032,0.023912,0.031939",\
9 x6 W- q0 e" h  Q               "0.004917,0.000010,0.004825");
7 @- K6 D5 ?1 j( O      }

0 s3 m" L6 w/ l* ]  q5 ?values是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?

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      fall_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("0.074043,0.058526,0.059156",\
               "0.152860,0.139810,0.137970",\
1 @5 R3 X7 Q, X0 T' C1 p: ?/ o               "0.231770,0.216260,0.216890");
      }
  v3 }; l% B4 M% x( p% l/ G    }

yytseng

internal_power() {
! y* p! Y) ~) T# t      power(POWER_7x1) {
        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
8 t+ E- X' b+ c        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
' n( R- z2 D6 c1 v: _1 v9 Dvalues值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?
- b- V1 K" S# G8 j% Z8 b/ h3 U8 i===> Wrong !
) X& H/ d0 ^1 S& X/ w  {  L===> they mean while different input slew (transition) of CK, results different internal power
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$ M( S+ O* q/ ]6 m* x, s3 E6 Smin_pulse_width_high : 0.061268;
, a/ y0 ]3 Q9 S+ G; vmin_pulse_width_low  : 0.125320;
CLK Hi/Low的長度?
====> No, these mean minimum possible of clock waveform to prevent functional fail, for high (1) and low (0)
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      index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
, H8 I( i% e/ x; |5 K4 }" N5 i, ~) \        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
      }
    }
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values值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?
==> No, index1 is often input transition. here represents input slew of D pin
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        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
" ]4 h# @, [1 r8 f& b        values("0.029659,0.026470,0.036963",\
               "0.032032,0.023912,0.031939",\
# ?$ A# s( u" q7 y% [1 ]1 p               "0.004917,0.000010,0.004825");
      }

  z$ O6 o  k! x8 _/ o6 [values是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?

: y9 b% Q7 c/ x" C1 T9 L, J6 T===> yes, but you have to refer index_2 definition in the front of liberty file to make sure.

霜淇淋

timing() {
      related_pin : "CK";
      sdf_edges   : both_edges;
      timing_type : hold_rising;
      rise_constraint(CONST_3x3) {
+ s0 \) f) \8 z' n5 D+ X) _5 S        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("-0.005932,-0.005209,-0.015703",\
               "0.013887,0.014610,0.004117",\
" W  e# l. ?) n4 z/ U               "0.060728,0.056519,0.043560");
      }
      fall_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
6 X$ `- k7 |2 W" f        index_2("0.006000,0.108000,0.217000");
' j; v  a: g5 N0 W# v. w( p: m        values("-0.018261,-0.002744,-0.005839",\
               "-0.028829,-0.021521,-0.028745",\
& `3 }. V- _* q3 W$ ^; a               "-0.004426,0.053203,-0.004342");
      }
# S$ w1 m( z0 f4 G7 G5 o0 O+ s8 {    }
  }
  pin(CK) {
    direction : input ;
7 y4 w7 {. s, Z0 j+ g8 f    capacitance : 0.001915;
+ V1 q  j* {5 `" h3 g) K    max_transition : 0.217000;
* H* j3 S  ^8 F    clock : true;
8 i( D1 z1 `8 w, q6 v' r$ [% x" L) Q/ D( z    internal_power() {
      power(POWER_7x1) {
        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
; H6 D& G/ b/ M        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
) x+ k1 z0 u1 z# ?; E& m) [6 \! C& B      }
    }


3 h& X: C4 J4 _' R# bvalues值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎?

    min_pulse_width_high : 0.061268;
7 _/ I' G& @" {0 t( M    min_pulse_width_low  : 0.125320;

CLK Hi/Low的長度?
+ d0 e: J" y* m( v  }
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有觀念誤解的話希望幫忙修正..謝謝
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[ 本帖最後由 霜淇淋 於 2009-9-17 02:03 AM 編輯 ]