請問由Verilog code到IC layout 需要哪些軟體

leesg

問題, 已完成 Verilog code 設計, 模擬(ModelSim)
( \- j" g" B! N6 j% p想要用軟體直接 run 到 IC Layout 產生 die photo,
要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)
1.
6 g& }. n( k8 ?design compiler + Astro ?

3 s/ h. _$ H+ |; x8 A2.
synopsys IC compiler ?
0 H+ a( H  E+ a: \3 j( R
3.
5 @+ e+ B& C0 t- @- u" Ncadnece virtuso ?

lee100

Synopsys R2G flow
' e( A: s) [7 j# S) l1. rtl simulation by vcs
2. synthesis by design compiler ultra with dc/dct mode
7 x1 p* N1 [2 O3. dft insertion by dft compiler
4. jtag insertion by bsd compiler
5. ICG insertion by power compiler
6. pre/post-layout STA by prime time
( y% f3 @, J! k% h$ G8 ?6 g3 {7. pre/post-layout power analysis by prime time px
, B9 k5 {) u: F: _  g8. PnR by IC compiler
9. post-layout SI analysis by prime time si
10. post-layout simulation by vcs

putechen

sometimes ,star-RCXT is necessary.just for layout PEX.

yytseng

after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.
- W2 a+ S7 k) u3 s; u- qclean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.

ejean

1. magma is another solution
2. Astro  from synopsys
3. FirstEncounter from Cadence
" b: D. z5 L) h- P1 n; b3 ?  f5 q  }
3 \9 n, ~; F2 e- a. xAll with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.

ilovepachaya

私心推薦APR使用IC Compiler  效果很好