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發表於 2010-10-27 17:23:41
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4.Are there any special thermal management concerns when using Stacked Silicon Interconnect technology? ! p0 N; _4 G& F& Q/ e% X
No. Because the interposer is passive, it does not dissipate any heat beyond what is consumed by the FPGA die. Stacked Silicon Interconnect technology FPGA devices are, therefore, comparable to a single die if such a large monolithic device could be manufactured. ) B4 P% \6 I! @7 F5 I
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5.Is Stacked Silicon Interconnect technology reliable? o. Y; z2 `) k/ G) D2 E' K4 J
Yes, in general, internal stress of Stacked Silicon Interconnect technology package architecture is lower than the equivalent size of monolithic flip-chip BGA package since the thin silicon interposer effectively decouples any internal stress build up. Therefore, thermo-mechanical performance improves by reducing maximum plastic strain in the package.
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* \% z7 U) f) }$ D2 H' r) ^6.Who is expected to use the FPGAs made with the Stacked Silicon Interconnect technology? V2 v# D5 A/ G$ ] Y
Customers in Communications, Medical, Test and Measurement, Aerospace and Defense, High Performance Computing, and ASIC prototyping (emulation) who are looking to implement their next-generation, most demanding applications with FPGAs are likely to benefit from the earlier availability of the most resource-rich FPGA devices. By not having to drive off-chip through I/Os (parallel or serial), across PCB traces to adjacent FPGAs, designers that have previously used multiple FPGAs in their system will appreciate the high-bandwidth, low-latency, power-efficient interconnect between the FPGA die. |
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