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Cadence ==> RTL Compiler + Encounter Test (acquired from IBM) - |! N# e1 l' v8 T0 M' o
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special capability:9 Q1 t0 |$ F8 C& l) J1 J
Synopsys : support multiple clock domain, phase shift test clock5 m; e$ }. J, C, A5 }. c8 F
Mentor : highest compression6 ~% U g+ g- K, f4 a0 Y0 k
Cadence : low power handling, pattern fault, diagnostics+ X- q2 D% d8 T9 y# {$ ]6 {5 E
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Common new features:! |% l. ~+ e+ y3 t+ m4 h0 ?6 ~! j
Compression, at-speed ATPG, core wrapper, BIST, IEEE1149.1
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In my image, Syntest had became a service-oriented company. |
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