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//some example0 ^/ d! m% K4 h& i. d3 R. k
2 j4 {, O; ]4 j
// define variable
( _* Y# ]$ J7 W" B# _% \VARIABLE RVM1 0.077 // Metal-1 resistor
! N3 T* `& M8 M3 ~+ X VVARIABLE RVM2 0.055 // Metal-2 resistor
( x9 r- J! n! C, VVARIABLE RVM3 0.055 // Metal-3 resistor
( L7 Q W/ x5 z$ r; J+ b: O# N
7 X. e; M% U6 v: M// lvs option4 r, i1 l* j9 z; t8 o4 s) w
LVS SPICE PREFER PINS YES
; M, i) t/ l; x' L# l/ GLVS ABORT ON SUPPLY ERROR NO
7 t* Y% L+ L% } |9 ]# B' dLVS ALL CAPACITOR PINS SWAPPABLE YES
. L, d" y) ?1 fLVS RECOGNIZE GATES NONE
' q1 | v9 z' c% B3 K# i; cLVS IGNORE PORTS NO
: f, K) z Z8 `. RLVS CHECK PORT NAMES YES+ R% q$ X! T# b0 H6 j1 L) e
LVS REDUCE PARALLEL BIPOLAR YES7 u$ k: e, J2 L9 r _+ f
LVS REDUCE PARALLEL MOS YES
0 Z/ E; n8 U; Q: q( N0 E ~5 C9 RLVS REDUCE PARALLEL DIODES YES; a. X. ?& z: \) T' M
LVS REDUCE PARALLEL CAPACITORS YES
+ T2 Y' y# h: `7 v% rLVS REDUCE PARALLEL RESISTORS YES
) R2 M# R7 J) N, H- b( Q! [LVS REDUCE SERIES RESISTORS YES //Smashes series resistors, k4 }/ f5 g$ \
LVS REDUCE SERIES CAPACITORS YES //Smashes series capacitors
; |1 N- p1 x* F: a8 e; CLVS REDUCE SPLIT GATES NO //Smashes MOS split-gates.) |) \2 [4 ?1 Q0 p
//LVS FILTER UNUSED OPTION B D E O) ? ]5 G$ J7 a( C; L" C( f5 \
LVS FILTER UNUSED OPTION AB RC RE RG
0 O' O* Q% ?5 ^5 PLVS PROPERTY RESOLUTION MAXIMUM 65536 // ALL6 Y- Z1 Z) _: d x w" x7 F
1 x" g \. t- g: m% x
// layer definition3 h* I$ G9 P0 j+ g6 q
LAYER DNW 1 // DNW -- Deep N-Well
7 M: a& x, U9 T1 [LAYER NTN 11 // Native Device Blocked Implant e; W3 P$ j/ @9 ], @) H2 K: r
LAYER NWELL 3 // NW -- N-Well: d- a! {- F4 z* D! H, `
LAYER OD 8 6 7 // OD -- Thin Oxide
2 p# M/ v% {5 {/ ~0 p# c0 V- x) I8 Y- b# M3 _# V ^
// layer operation
, V5 I/ ^+ m6 s6 w2 ^: `rpolywo1 = POLYG AND RHDMY 9 [8 {$ S6 \* W6 `& ?& o p
rpolywo2 = rpolywo1 AND RPO
2 I n% R* [& i3 N4 Hdiff = OD NOT RODMY " O8 _0 Z; h2 U6 ~8 a) m
rp1 = RPDMY NOT INTERACT diff / V# J* q1 I2 [) I1 ^6 M
p1rdum = rp1 INTERACT POLYG8 x6 @- Q0 d7 T; M! T# a
8 n5 R Q" g1 k+ s; g* t// connect statement
; y4 ?8 o7 r' RCONNECT metal1 c2poly BY pl2co; M/ A4 G( \$ ^, D: x5 d
CONNECT metal1 tndiff BY pl1co0 @! _9 d# Y3 V9 \
CONNECT metal1 poly BY pl1co
; z7 f2 N( j- l" U) SCONNECT metal1 tpdiff BY pl1co
/ W8 J& A# \) sCONNECT metal2 metal1 BY VIA1
3 K$ J: `" B, [- u. iCONNECT metal3 metal2 BY VIA2+ L& a& H! ]2 t* `: X! E% Z: J+ S7 ^
CONNECT metal4 metal3 BY VIA3$ R) |7 P- _: w8 B& l; G9 n9 h
CONNECT metal5 metal4 BY VIA4
9 [+ r2 C" I& u/ ]6 Y7 F6 s) JCONNECT metal6 metal5 BY VIA5* u* A, i7 X' Z; K) F& C
CONNECT metal7 metal6 BY VIA6+ s2 O" L3 K1 p0 R- ^
CONNECT metal8 metal7 BY VIA7" ~/ b, C S' T4 m6 N# a S4 U
CONNECT metal8 CTM_M7 BY CV7
6 ^) F# j( O5 W5 G& ~8 q* j. N. t* b. \1 o4 U* |9 U
// device definition
$ e8 l1 v+ }+ NDEVICE MN(nmos) nmos poly(G) ndiff(S) ndiff(D) psub(B) [' j. f' k" R. i8 S- C: x
property W,L
' J- ?( I+ O* I: \! b; k W=(perimeter_coincide(nmos, ndiff ) + perimeter_inside(nmos, ndiff)) / 2/ r$ l, d! v: z" ~( [# `
L=area(nmos) / W! Q( |, S2 }2 [$ E
]% I2 V2 s: n( B9 K$ y; v
: H! ^* q: {& x3 j% _
// trace property
) d$ v8 }7 y* p3 yTRACE PROPERTY MN(nmos) L L 08 D9 h* @ }1 x) I. K: [% F5 w
TRACE PROPERTY MN(nmos) W W 0 |
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