FPGA verification Engineer most difficult job functions?

ranica

Staff Verification Engineer

& |9 e# _5 M! M& P公      司：one famous IC company
4 C- V. ^- a' g" r工作地点：上海

Qualifications
MS in EE/CS/ME.  
Minimum of five  years experience.
# g& \0 @" ^& z, d# l/ \Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
! Q3 \& U; a2 i7 J" ]$ F! t5 ZCandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
/ E9 G1 b( G* U2 R" `, I' xCandidate should be familiar with industry standard ASIC design and verification tools and flow.
' z, _5 z: j2 T$ x- u! w. oGood knowledge ddr protocol and computer system achitecture would be an added advantage.
) [  X5 E! Y7 Y9 ^Good knowledge of Perl and shell programming would be an added advantage.  

0 n" T: j5 }# J+ w1 Q- _Responsibilities:
-Understanding the expected functionality of designs.
8 s) R% A- }& c-Developing testing and regression plans.
-Designing and developing verification environment.
/ v# K) m8 r1 j8 A* Z1 E-Running RTL and gate-level simulations/regression.
5 w" K6 W2 s. c2 v1 v! w! ^9 P-Code/functional coverage development, analysis and closure.

4 m0 T0 ~( c- g8 q6 C' XRequirements:
. r/ Y7 N1 Y. @+ DExperience & Skill: 5 Years
; Y5 y' {5 v( k# d; z5 o: j-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
8 Y3 X; P' X! a' y  k-Knowledge in ASIC/FPGA design process and verification tools.
+ z. n% u8 P! }) U1 w! p-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
  ~! Q+ G1 e( ]-Familiar with C/C++.
' M  p. V* I" p" C-Knowledge of DDR protocol a plus.
* n, v3 D: e! k0 p; b3 j# f-Independent and self-managing.

ranica

Digital Design Engineer
3 }% D) x5 G8 \( K/ J$ k( F
公      司：A famous IC company
/ `+ a. q6 r/ m3 K工作地点：上海

Duties
3 j; G$ w( v; F5 v8 ^Work with internal and external customers to understand product requirements.
Create critical silicon technologies to meet the product requirements.
Work out critical design flows and methodologies to execute implementation flawlessly.
" x* X  z# h: V& Y8 W6 e. L" XDesign and deliver final design through multiple stages like specification, micro-architecture, IP  development, RTL coding, verification, logic synthesis, DFT, timing convergence, as well as helping on physical implementation.
' e. F6 z- y& }0 qComplete full documentation.
( c% B" {  g; u" fHelp and mentor junior engineers.

0 t  ^$ w; `, m; CJob Requirements:  
Solid understanding of all SoC chip development stages is required.  
Hands-on Experience with complex SoC design flow is required.  
! X# E2 n" B8 F/ L8 a7 n* f3 e7 uHands-on Experience with RTL coding, simulation, verification is required.
Experience with DFT and timing tools is preferred.
6 R$ b* w/ C- t# s+ U7 v7 G6 eExperience with ARM platform is preferred.
Experience with low power design flow is preferred.
Experience with system verilog is preferred.
( V" o( b% ]. {+ Y2 {: o, L; vGood organization and documentation abilities  
9 T8 c. H8 ~4 s$ y( n" J1 _2 DMS in Electrical Engineering and Computer Science with 4 years of experience in SoC design

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