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//可直接透過synthesis tool用於PLD,FPGA不可 LUT delay則要採其他方式。
! J4 D' o/ r: g; k7 x @; G//所有註解都要保留+ s9 p4 s& r1 N) i% }* Y" f/ a
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`timescale 1 ns / 1 ns
" m' T3 N- |% ^$ Zmodule xclk(sclk,ena,set,outp);
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7 a2 ?- S( X+ \$ E Cinput sclk,ena;
& R% u. `" l- i3 R5 d+ X$ {. ~3 dinput [1:0]set;
5 ^- e/ a, I7 M, F3 p6 toutput outp; ) z; L* x# f# a. i* o2 ^
' f/ ^" J( O' ~3 X& N# Lwire outp;8 \9 l- n q6 t. e. [
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/**** Node preservation for nodeA **************/# k$ }- W% [* t* }( @4 S2 T+ A% g
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//exemplar attribute nodeA_5 preserve_signal true
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' {' S- W0 K) g, h1 m, Z y/ o//exemplar attribute nodeA_4 opt keep
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, @9 F2 n3 u% T( g( w4 e3 K/**** The following comment form also works ****/
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3 p/ [, W1 M. V9 u2 T//exemplar attribute nodeA_3 preserve_signal true) C+ n8 ^ H3 J5 k: P+ ^( B1 Y
/ q; B5 d3 f+ h; {9 C//exemplar attribute nodeA_3 opt keep
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3 V: i! I- Z* R4 ]" z/ O( o. _/**** The following comment form also works ****/) @ x0 Z8 Q( l1 P0 t( s4 j3 h/ q
. S' C7 j/ ?: T& l& H' C5 i//exemplar attribute nodeA_2 preserve_signal true: w; I8 p; G4 Q
b" ]% _! ?0 l; m" @//exemplar attribute nodeA_2 opt keep
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8 x0 L0 P& Z3 D/ i) ?/ Q/**** The following comment form also works ****/$ X! h# z/ a( f8 D
* @1 M0 {: ]+ L' ?- @//exemplar attribute nodeA_1 preserve_signal true
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//exemplar attribute nodeA_1 opt keep
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/**** The following comment form also works ****/; B! a0 y# Y" p3 s# c
5 u# C1 f3 [' }" v) W) X/*exemplar attribute nodeA_0 preserve_signal true
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exemplar attribute nodeA_0 opt keep*/ 4 \5 G6 D' W9 m9 Y
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wire nodeA/* synthesis syn_keep=1 opt="keep"*/;
! t0 x0 g4 z( Y! w( p" Jwire nodeA_0/* synthesis syn_keep=1 opt="keep"*/;
4 \! J* R; Y( h/ X7 _' Swire nodeA_1/* synthesis syn_keep=1 opt="keep"*/;
& w0 y/ H$ U; s7 xwire nodeA_2/* synthesis syn_keep=1 opt="keep"*/;4 ~9 D M! j) e( u/ M( [% x7 E
wire nodeA_3/* synthesis syn_keep=1 opt="keep"*/;
; y8 E8 s& B. Q: Qwire nodeA_4/* synthesis syn_keep=1 opt="keep"*/;
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7 c3 r' @5 E9 H" P; m! u& n% dassign#1 nodeA_0 = sclk & ena;4 j. U f) P9 r- `5 U: _% O
1 J5 W% `0 [+ ^% d/ m6 Y) Rassign#1 nodeA_1 = ~ nodeA_0;
2 ~5 p: O$ U6 w/ v1 b' p8 n! Bassign#1 nodeA_2 = ~ nodeA_1;& x- ]% B; O2 b) `* p! A2 T
assign#1 nodeA_3 = ~ nodeA_2;
S9 c0 X3 o3 v0 N! r ~: z1 b/ Iassign#1 nodeA_4 = ~ nodeA_3;
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* w' F; {1 ?0 v4 Creg xout;" E% _( E& J, s4 ?+ v4 M
5 D4 A' E R7 e6 D& g1 V1 G3 s Calways@(nodeA_1,nodeA_2,nodeA_3,nodeA_4,set)
1 B* s. K3 H' v, y1 I3 x/ E& M+ P casez(set)
3 ?, ^ C" g( W& u 1: xout =#1 nodeA_2;
2 U* b. ~( S( ] 2: xout =#1 nodeA_3;
+ `1 {0 G* K) G& K2 Q; k 3: xout =#1 nodeA_4;" {, t) E5 l+ ?
default: xout =#1 nodeA_1;
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( c7 F3 y: |0 M& X6 i1 sassign#1 nodeA = xout;' B( f; V1 l1 ?6 f) h& q
assign#1 outp = ena ? nodeA^sclk : 1'bz;
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. t9 H: N8 j& S0 v+ ^7 Kendmodule8 }& Z5 h! M* N2 M0 Z9 s
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`timescale 1 ns / 1 ns
! X' {$ ~ [1 g: D% T6 p+ E% _module xclk_tf();0 R, f+ y+ @' U; v: |) X j/ I
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// Inputs
) i, `3 e4 v0 b5 G% Q E9 Z* n6 i" E reg sclk;& Z) f! a9 F8 Y* D/ i
reg ena;8 d, c9 u$ A8 H: M
reg [1:0] set;3 q) c& H- O% w# M O" e5 d* x+ ^
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// Outputs' p- l- K. Q+ V# a% \
wire outp;
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: m, Y3 W- O6 J% f( _ xclk UUT (7 V+ d& H# r0 n! A; s: [
.sclk(sclk),
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.set(set),
9 C4 T8 _3 n" O f. n .outp(outp)# }0 S* q4 ]: `' F, L0 Q
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sclk = 0;# G; p) Q0 q5 M& z t0 f
ena = 0;+ x9 H0 X8 f8 e# n
set = 0;5 N+ Q3 Z6 C i* ^$ [$ S
end
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always# 5 sclk = !sclk;
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#100
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#2000
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set = 3;8 p" k; s; M; N% P& c R
#2000
1 T! a5 b) z) y% R) O4 ~ $finish;
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endmodule // xclk_tf |
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