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0. Check circuit topology and connectivity.
( I* m* X3 r6 e, U. }+ KThis item is the same as item 0 in the DC analysis.$ p" L/ K$ _# w% _* C
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1. Set RELTOL=.01 in the .OPTIONS statement.
- j @* z9 h4 f8 k: l% w) fExample: .OPTIONS RELTOL=.01
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; {& h: d; y/ b; q2 D5 ~' J, l2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
! j: i8 z) G, f9 i3 Q: Q) C0 k$ b$ PExample: . OPTION ABSTOL=1N VNTOL=1M
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/ E7 W# h; Y N$ H3 c/ R3. Set ITL4=500 in the .OPTIONS statement.
' Z1 f4 Q' e% g7 {- rExample: .OPTIONS ITL4=500
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4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.
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5. Reduce the rise/fall times of the PULSE sources., {# u$ g, f$ q# o. G' [
Example: VCC 1 0 PULSE 0 1 0 0 0
* P4 \* Q% }7 U ubecomes VCC 1 0 PULSE 0 1 0 1U 1U: ^& M \6 r1 a$ O1 g0 t& \& u
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6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.
9 J2 Z) _2 [2 c \7 i; x M8 I2 MExample: .OPTIONS RAMPTIME=10NS
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7. Add UIC (Use Initial Conditions) to the .TRAN line., \: z, n9 z4 g% e
Example: .TRAN .1N 100N UIC* r( S6 c1 d, N& a+ a& A
' n6 X7 }3 N/ H: o3 I4 `! C1 Z8. Change the integration method to Gear (See also Special Cases below).# C' Z9 w/ q6 l4 P6 V, R0 G% d
Example: .OPTIONS METHOD=GEAR |
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