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AMD Geode LX 800@0.9W處理器
General Features" |$ H, W0 |" y8 Z0 D% p
■ Functional blocks include:, [, r( M; `6 K w- V2 G
— CPU Core7 z! A1 Z3 t5 _" p( F: Y
— GeodeLink™ Control Processor. B4 h; ?) L7 Q, o/ P
— GeodeLink Interface Units; m- }" V. ^1 e
— GeodeLink Memory Controller( ]4 p( S% f: O, [3 L. b- i8 ]6 n
— Graphics Processor
. _. h; m' r5 M, O& D1 J/ I6 M— Display Controller
; B1 T. B0 q/ N" ]) ] ]— Video Processor
# k5 n0 J+ n/ Q w– TFT Controller/Video Output Port# Y+ P9 x- \' }* u9 J0 O
— Video Input Port$ r9 s. }- a2 c6 o
— GeodeLink PCI Bridge
; ~" i. Y/ j: H" n: l' W— Security Block
2 B3 Q: y5 b8 g, o( W■ 0.13 micron process
! x$ H2 d. `7 X$ w+ n: u3 K■ Packaging:
$ O4 Y+ `" D8 v# p" p6 S— 481-Terminal BGU (Ball Grid Array Cavity Up) with8 x- \3 G) I4 d6 h# H; `
internal heatspreader! G7 [4 j3 F- \, |' t6 C3 H# K
■ Single packaging option supports all features- Z' P5 R: T! s8 S, f9 s; K& `
CPU Processor Features
9 @/ z; ^' I1 s; Q( @% d* U a4 c■ x86/x87-compatible CPU core
! e1 ^' c: s6 Q0 W9 K3 U7 F6 E! }■ Performance:2 G7 t) H. O Z
— Processor frequency: up to 500 MHz+ P" P; S6 i( R+ p3 [7 }
— Dhrystone 2.1 MIPs: 150 to 4507 X. b: D, H ?9 x, h" E
— Fully pipelined FPU9 M8 I% o+ b1 v- J6 x+ J: J
■ Split I/D cache/TLB (Translation Look-aside Buffer):# z2 T& \( Q+ W8 t: k$ x& u
— 64 KB I-cache/64 KB D-cache
/ j& L4 W {+ _! r— 128 KB L2 cache configurable as I-cache, D-cache,
0 B& B8 L/ ~% @2 I# A/ \4 ^or both
F0 O5 m- k* A% W* y# l■ Efficient prefetch and branch prediction
! Y9 a; q" x2 Q7 W8 d■ Integrated FPU that supports the MMX® and; [" Y' H& ` _+ a( o$ j
AMD 3DNow!™ instruction sets
2 Z) ?% `+ _) K* x# f' R6 M■ Fully pipelined single precision FPU hardware with
, T8 ?- ]9 \1 L* ~& I' {+ Nmicrocode support for higher precisions
g( c& d/ F/ WGeodeLink™ Control Processor5 _7 ~( y6 h; m3 T) O3 D9 {
■ JTAG interface:1 @1 ?9 S7 b; K4 A8 R9 F
— ATPG, Full Scan, BIST on all arrays4 v) I; u+ W8 D$ S$ F
— 1149.1 Boundary Scan compliant. J2 Z* H# [+ \3 a
■ ICE (in-circuit emulator) interface
' m( U/ t: ~8 Y3 [. c: h■ Reset and clock control$ n: O% }" d L3 s9 c& z- F) l
■ Designed for improved software debug methods and
1 N+ r8 d" J% {! A9 }4 o# p* `. `performance analysis
3 R$ |' v6 S- \' a. A■ Power Management:& U1 x, m0 x: v8 W, B
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
+ f7 ^- @' U3 Z3 L' D2 x9 u500 MHz max power" r( y4 q' h6 G: P3 Z8 J
— GeodeLink active hardware power management6 ~+ l4 Y1 @* q) W1 D0 Q
— Hardware support for standard ACPI software power, L( F- I; m; N3 q$ Y& g
management
+ f: O' Q0 F- @3 t— I/O companion SUSP/SUSPA power controls2 e ~$ m# i4 f7 Z9 W( i5 r
— Lower power I/O! x2 g3 x7 m4 Q* u& |
— Wakeup on SMI/INTR# J, T/ I! C/ g0 F* s
■ Designed to work in conjunction with the; Q7 {* }8 y# |9 p; W5 k
AMD Geode™ CS5536 companion device
: B: `# W% U: Q) J8 j5 eGeodeLink™ Architecture
$ P0 }/ j) d: \. ?7 R- Q5 k: k■ High bandwidth packetized uni-directional bus for/ q; X" e- `9 N4 n+ c8 y" O1 K
internal peripherals0 W* g, x# o7 Z4 [
■ Standardized protocol to allow variants of products to be4 h: v- ~1 m& L% E. `
developed by adding or removing modules% ]$ O- x+ L3 \0 `
■ GeodeLink Control Processor (GLCP) for diagnostics, R! e+ M; ?& M! D1 G/ b
and scan control
$ ]* q, Z/ M' S■ Dual GeodeLink Interface Units (GLIUs) for device interconnect& } d' }; v8 Z+ x
GeodeLink™ Memory Controller, @! w: ^# \3 \( J7 L
■ Integrated memory controller for low latency to CPU and
, r' n0 K& K$ `; O8 g6 Kon-chip peripherals
& D& E# _% ~6 g+ H6 d) f■ 64-bit wide DDR SDRAM bus operating frequency:
7 Z& c1 R# W8 T9 X v' a' U— 200 MHz, 400 MT/S
( _% |7 ?* ^ |( j$ e■ Supports unbuffered DDR DIMMS using up to 1 GB! ~# e4 E3 m2 ^" l4 U9 Y/ L+ V
DRAM technology
+ G. d) ^2 {: ~+ Q) l■ Supports up to 2 DIMMS (16 devices max)
+ h W E/ W' x$ w% X2D Graphics Processor3 f& v! I1 R; z7 e* ~
■ High performance 2D graphics controller$ k7 I# c0 B7 K, p6 o
■ Alpha BLT
( q6 \: i- ^7 X/ |: X■ Microsoft® Windows® GDI GUI acceleration:$ | f& Q4 w1 ]6 Y. U4 [* e
— Hardware support for all Microsoft RDP codes" ]- W. }( b% }- f
■ Command buffer interface for asynchronous BLTs
8 ?% X j; i$ J, a$ F4 [■ Second pattern channel support( t& @- c+ G) r$ S3 w) E
■ Hardware screen rotation |
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發表於 2007-2-6 18:17:18
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