ASIC設計工程師如何保住飯碗？

innoing123

Junior Physical Design Engineer
3 V5 c+ g4 `  v, `! X+ K公      司：A famous IC company
工作地点：北京
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% s+ {3 M0 a% s: W. gPosition Tasks, Duties and Responsibilities
" K! R7 U) u' z) _/ D1 QThe ASIC Physical Design Engineer will:
1 V* A$ Y6 w8 ?, U, k9 k9 |& n        Complete third party IP integration and ensure vendor guidelines are followed.
* m$ L2 u: O0 o5 d' w( b        Responsible for physical verification (DRC/LVS).
# v/ w; G2 h# K  I        IO ring design, fullchip floorplan.
        Block level implementation.
        Work with front-end engineers to resolve problems and achieve design closure.

Candidate Qualifications:
Candidate must:
$ d! w6 }$ Q1 ]        Hold BSEE (MS preferred).
        Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
        Be able to complete block and chip level tapeout quality LVS and  LVS and DRC.
' u7 h: P* Z7 z+ L        Have the ability to independently identify and resolve design, tool, and flow problems.
        Have related timing and physical concept.
2 X6 [  e! E4 |, H+ _5 D( D) k" F# w        Be able to design and implement physical design strategies and methodologies for deep submicron designs.
* B8 P* E& P/ y. I* W        Familiar with EDA tools.
% i+ x" Z( \' b# x  b        Familiar with Linux environments.  
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Any of the following is beneficial:
# N1 ]9 H3 M# t) e& v        STA constraint design
1 m. K; {7 K. v( F: x' ^4 }       Equivalence checking ?RTL to gates, and gates to gates.