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Senior Digital Design Engineer- D8 t, L T: H
& B! {5 D6 N9 y6 ]0 y4 {公 司:A leading semiconductor company% ~9 h5 g, C! y: [% [
工作地点:香港8 E; h3 F1 B+ n4 o8 I; } O
9 X8 y Z: b+ J! l) cJob Responsibilities: 1 J7 |7 V$ l5 S0 P% \
Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
4 N o2 k; e7 w0 D+ j Develop verification environment and coverage closure
8 r* G$ y* k9 c. J2 b Support wafer level testing and silicon evaluation
* Q* J) f* C' K- e5 s Prepare technical documents! L: B7 [3 g- N1 ~5 f( N. n n
k2 n! I( C( h* r, yJob Requirements:
8 A: [( R- A5 e3 C1 n B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage p% g! z) G7 B6 [, p
5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations ! o8 L& `3 g! ~3 @
Knowledge of SoC and embedded system. / {0 e/ w! d) a! h% p1 s# C- a
Knowledge of scripting languages such as Perl, TCL and Make 2 ?# U3 x4 h* _8 D( t: u1 L" `
Candidate with less experience will be considered as Digital Design Engineer |
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