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Agenda | Time | Topic | Presenter | 09:00 ~ 09:30 | Registration | 09:30 ~ 09:35 | Welcome | Apache | 09:35 ~ 10:20 | Message from Apache and ANSYS | $ w6 y; T6 Z0 D
Andrew Yang, Apache3 l3 F7 h* ?. Q; r, d: [ ]: c. \
Chuck Yuan, ANSYS | 10:20 ~ 11:05 | TSMC Keynote | Dr. Bing Sheu,TSMC | 11:05 ~ 11:50 | Power Artist RTL Power Estimation Experience Sharing | Steven Chen, Broadcom | 11:50 ~ 12:50 | Lunch | 12:50 ~ 13:20 | Apache Product Overview and Update | Dian Yang, Apache | 13:20 ~ 13:50 | ANSYS Electronics Product Overview | Jack Wu, ANSYS | 13:50 ~ 14:35 | Coalition of Chip Package Co-simulation to Fortify System Level Power Integrity | Ricky Yong, Mediatek | 14:35 ~ 14:55 | Break | 14:55 ~ 15:40 | ASE/Apache JDP – A Novel IC Design Platform for
! o. ?+ D0 Y# Q r* N8 MDynamic Power Noise Validation with IC Package Model
3 M+ s1 a3 G5 |) F5 p' g | Dr. Chen-Chao Wang, ASE | 15:40 ~ 16:25 |
+ M' r1 h; |0 A# KDesign Challenges for 28nm and Beyond | Henry Lee, Apache | 16:25 ~ 16:45 | Wrap-up, Lucky Draw |
※ 備註: 主辦單位保留變更議程順序、內容及相關事項之權利。 |
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, n8 T F$ J) i# K參加研討會,還有機會抽中Apple iPad2唷! |
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