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CMOS Transistor Layout
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7 G7 R7 W- D9 bCopyright © 2005
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6 f7 C+ x; J7 i4 i1 c9 ^Table of Contents
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+ _. \( K1 U! jPreface# {" H9 A, a$ {9 s
1. Introduction .................................................................. 1
. g4 u" `& u! k( }: z2. MOS Transistors ........................................................... 2
3 P7 I2 q8 m7 q7 S6 `+ S% D" j# ~3. Fabrication of MOS Transistor ..................................... 56 p: I6 p [/ n2 A
4. Layout a Single Transistor .......................................... 11
. Z: Y+ `. v) J6 a9 c/ m: g# nFirst Stroke The basic transistor layout ..................... 12( c. R- t X* G+ s* d4 ]# _$ x$ J
Second Stroke Compact the transistor layout ................ 13
! b& \% _0 s/ f& V5 I2 O& `/ GThird Stroke Speed up the transistor ........................... 17
" n9 f& ]/ ^5 {/ BFourth Stroke Clean up the substrate Disturbances ...... 203 j# J9 \1 S$ u# S7 w
Fifth Stroke Balancing area, speed and noise ............ 26, J5 G6 P$ @3 ~4 @, }
Sixth Stroke Relief the stress ...................................... 29& _, U4 [! p- R9 {& D9 v! A* n
Seventh Stroke Protect the gate ...................................... 309 z; {! e: E% C
Eighth Stroke Improve yield ..........................................328 N# G3 b% l4 c' B
5. Layout Several Transistors ......................................... 34) Z6 X8 E9 ]0 b+ O* f |2 e
Eighth Stroke Improve yield...........................................35
A0 k4 I" m, X RRe-visit
6 e# _0 z+ C9 r2 I' K1 l0 aNinth Stroke Close proximity .......................................36
, a R; w$ {( y$ ` F( jTenth Stroke Interdigitated layout ............................... 36- Y7 \' i5 L0 N: p' `4 H% `
Eleventh Stroke Dummy transistor ................................... 413 y( D" z6 Z1 ?2 S6 t0 M3 L4 m7 ~
Twelfth Stroke Two-dimension interdigitated layout ..... 43
8 p, G5 o$ y! b3 eThirteenth Stroke Guard ring for the matched transistors ... 45
) C- X8 \- u+ k9 ?# |$ ?Fourteenth Stroke Keep NMOS away from N-well ............ 45
6 S6 ^1 X( O! s; I5 o8 ]Fifteenth Stroke Orientate the transistor ........................... 466 j2 q( U% Z) K+ U3 l
Sixteenth Stroke Match the interconnects ......................... 476 \1 ]0 Q6 |' g8 d& {9 u" A1 A& L* H, e
Seventeenth Stroke The unmatchable .................................... 501 Z3 j1 i/ T F. s1 d" l6 h% u
6. Verifying the Transistor Layout ................................. 521 H$ w% {, i( e7 u T
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[ 本帖最後由 semico_ljj 於 2008-11-1 04:01 PM 編輯 ] |
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