FPGA verification Engineer most difficult job functions?

ranica

招聘公司：a top 15 semiconductor company
招聘岗位：Product Engineer
8 I/ `, |/ ~$ {工作地点：Beijing
$ Y* v: _9 t9 [& M3 e
6 u, Z8 L( x3 _$ ]( n  E' o岗位描述：
- m. j# y1 E$ R; R/ F- \2 v- Design database verification by simulation and on FPGA - Chip function evaluation - Develop test firmware and tools (Hardware and Software) - Develop evaluation board - Cooperate to debug chip issues - Customer support • Assist with customers’ issues • Visit customers and provide on-site support • Build up demo system

  ]% i& E  G9 T/ V# f职位要求：
- BSEE or above with minimum 3 years communication system experience - Familiar with Verilog. Has digital design experience with Verilog in real project - Minimum 3 years FPGA working experience, including code writing, timing analysis, debug - Familiar with at least one of schematic and PCB layout tools - Excellent English skill will be required. - Strong inter-personal, teamwork and communicational skills

ranica

客户 A famous IC company
4 g( z& @) F- q7 P' p; m* t: M; }地点 Shanghai
& R( o2 `2 I& g' E# q# `5 X
职位描述
We are looking for a person to join a design team to execute a state-of-the-art IC design project in the wireless communication field. Candidate must be familiar with digital IC design flow with a proven record of design and verification of a complex design project that led to successful silicon. Proficiency in Verilog is required.
  I) {2 H9 A% [1 ^, L$ C( l
职位要求
Experience in the following areas of expertise is desired:
Wireless media access control (MAC) design experience would be highly desirable
1 \# J5 _! m1 P' XKnowledge of TCP/IP and DMA Offload Engine design experience will be a plus
6 p+ Q2 j) O+ J3 i, C, j( |6 O  nRTL design, verification, and chip integration
Experience in the following is beneficial but not necessary requirement:
2 @! q( c9 S. J+ ]& aCommunication systems and RF systems
/ `7 r% n1 y2 P4 @# k. v: z; P4 V- n% rFamiliarity with wireless communication systems and standards (802.11b/g/n and WiGig)
% A+ F! d$ y  I2 cKnowledge of interface protocols such as PCI/PCIe would be a plus
FPGA design flow, testing, and emulation bringup

' ]% l" y- A# F2 e  k" K$ d7 M  VOther requirements:
Familiar with design and verification languages, EDA tools and ASIC/SOC design methodology
, v. t) [" U1 }$ ?Good script language skill, such as Perl, Tcl and Shell
Good written and oral communication skills in English
Good Team player
3 ]8 S# Q; Z& e  v( x: @5 m9 J9 W, vCandidates must have MSEE degree with at least 5 years of experience

ranica

招聘公司：A famous IC company
招聘岗位：高级ASIC设计工程师
' j+ X1 p# F# H工作地点：Shanghai
4 X7 t- K# f( x* _6 f* c  }
- m) I- F, a. P; O6 Y; Q岗位描述：
1、定义设计模块结构并编写芯片设计规范； 2、使用VHDL/Verilog编写逻辑模块的RTL代码； 3、编写测试向量对模块进行仿真验证； 4、在FPGA平台上进行芯片级的测试验证； 5、进行模块级的芯片综合与时序分析； 6、编写完整的设计和验证报告。

9 g8 `1 }4 X: g5 K1 H职位要求：
1、具有电子或通信工程类硕士以上学历； 2、 熟练运用Verilog/VHDL进行芯片前端设计，熟练运用设计仿真综合和测试工具，如quartus，Xilinx，modelsim，nc，debussy，逻辑分析仪，信道仿真设备等； 3、深刻理解数字电路设计和时序分析方法，并拥有故障定位和解决问题的能力； 4、深刻理解通信原理、数字信号处理等基础知识，熟悉无线通信原理与常用算法； 5、具有3年以上芯片设计经验，拥有无线通信物理层开发项目（如DTMB、CMMB、DVB、3G, LTE等）经验者优先； 6、工作认真严谨，积极上进； 7、良好的团队合作意识和沟通能力。

ranica

Verification Engineer
( [8 |4 Q7 a; c& Y# Z2 l+ U! v
公      司：A famous IC company
; r  [) o1 ~. X6 a  R3 t; E: a  L工作地点：上海

* O& c5 h: z$ x5 bThe Role:
3 a# _1 r9 n8 Z* L2 X5 m·         ASIC  verification
& }. I; a+ k# u6 d% `1 k6 `·         Work closely with the California teams
·         Support chip tape out and bring up

Requirements:
8 k2 M+ S5 S! }·         3+ years experience in ASIC Verification
+ T# e& M$ L* A0 n% @) M" J7 U·         BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
& F5 N1 s# {  X7 {·         System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification
·         Very familiar with verification languages – Verilog, System-Verilog, and VMM
·         Test plan and test case documentation
·         Functional coverage and code coverage analysis
8 {) J$ b0 R- {8 g0 V: [! V·         Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.
% p; B  F# q9 a$ K9 k% }7 ]4 h# j·         Experience verifying interfaces such as PCIe, Ethernet, DDR, USB
8 R2 k: C  O4 _6 b% d·         Working knowledge of networking protocols 802.3 and 802.11, especially Medium Access Control and TCP/IP
3 ?. g& _: E( L* V) n, o- }) w·         Working knowledge of C programming language
  I( C' z. W1 l4 M7 n* J8 B: v·         Must be familiar with the ASIC verification flow from feature identification to test bench development and through final tape out sign-off
; @) m9 }; C4 \  I, }! d: C·         FPGA emulation experience a plus
3 g% d  _5 O' T6 a- H6 \; y·         Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging

ranica

ASIC Digital Verification Engineer
公      司：A mobile chipset semiconductor company
工作地点：上海
$ w* d: N' V9 ^* d0 W3 L6 Y
Responsibilities:  
  Make verification plan for one module or whole chip.  
  Build up and maintain module-level and chip-level verification environment  
  Verify ASIC digital design based on case list, and output verification report.  
  Also responsible for lint checking and formal verification.  
% @/ \3 J  A6 ~- l5 {  {
Qualifications:  
  Proficiency in logic verification.  
  Experience with Verilog logic design language.  
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
1 A1 G. Q* q0 ~+ z3 g  Experience with C and C++ is a plus.  
  Experience with C_SHELL, TCL or PERL is a plus.  
  Experience with UVM, OVM or VMM is a plus.  
+ e# @1 _( y7 l  Good knowledge of SOC design is a plus.  
# i6 E6 X  \7 }# {& U1 V  Good knowledge of software design is a plus.  
1 t. V/ D" _! i& m& g  |% P) E+ G, s  Self-motivated and good team player.  
  MSEE or BSEE with 2+ years.

ranica

Senior Digital Design Engineer
公      司：A leading semiconductor company
  X# k" a* g0 i% S工作地点：香港
0 e/ |: Y  F  F* n
Job Responsibilities:
    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
    Develop verification environment and coverage closure
    Support wafer level testing and silicon evaluation
    Prepare technical documents

  p9 V. E% o) sJob Requirements:
4 t) ~: }5 l$ w0 Q    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
, h; z8 T9 w! B- i9 Y  G    Knowledge of SoC and embedded system.
    Knowledge of scripting languages such as Perl, TCL and Make
4 E6 f1 ^0 m1 V3 T    Candidate with less experience will be considered as Digital Design Engineer

ranica

数字IC验证工程师
5 M# y4 _+ B5 b* ]  U公      司：A famous IC company
工作地点：上海

% `& _+ E+ S8 K8 E岗位职责：
4 V! P- X0 U6 W1 C/ t1、负责整个团队验证平台的搭建、维护
4 @" ^4 c- E2 s9 U( U2、先进验证方法和验证平台的评估、导入
3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。
' c4 b: j4 m$ _
职位要求：
4 p: V$ S% j3 F4 D) g1、大学本科及以上学历，电子、通信、计算机或微电子专业；
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
# m4 P  u; k. G  ]3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
3、有1~2年芯片验证的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

Senior Digital Design Engineer
0 ~1 j: \1 y" V  ^公      司：A famous European IC company
" w6 y7 t- X8 _1 a工作地点：上海
7 ]/ m- n3 N0 m* I3 i; B
Job description  
+ z* [/ k2 H' N$ b- define system partitioning of s/c circuits and system  
- define HW/SW co-partitioning  
- provide technical feasibilities based on system simulation and/or FPGA based demonstrator  
- propose new technical solutions on s/c and system level  
- design digital part of mixed signal (smart power) ASICs  
- close cooperation and interaction with international teams  
- coach junior engineers  

" i+ C/ q) }' e+ p, g9 [4 iRequired knowledge competencies and attributes  
$ u; I" I& n+ D2 O- master degree in microelectronic circuits or systems, Communications, Computer Engineering (or equivalent)
3 o: ~" N/ k9 {+ r" q- > 5ys experience in digital design  
) J5 t; l9 t! f$ R# Q0 m$ r- good understanding of ASIC mixed signal flow (Cadence based)  
# C4 }, v/ R, p7 B4 h' b; P- strong background in HDL coding, verification and toplevel integration  
- q" P4 z% Y5 k) Y9 t- good understanding of communication interfaces used in Automotive (SPI, CAN, LIN, Flexray)  
5 S6 I$ O8 d9 e: i5 @- experience in FPGA development  
- very good communication skills (written, oral)  
( _. {, q; v( x* X  n0 m2 }: C- self motivated and high level of flexibility  
- N; O' J% X; _! ~- foreign languages: English, German (not a must)

ranica

ASIC Verification Engineer (WMAC)
公      司：A famous IC company
2 g+ Y, k! k% X" d6 _$ d! ]! Q工作地点：上海
: ?+ l0 G" e  E) H7 ?) P* U" w" p5 V+ c
7 n' q1 o6 V8 ^% X" O! v) {4 FThe Role:
4 u0 G+ R# [: U9 n# G, K+ o5 z% [        ASIC design and verification
; b, U3 L' k( R0 I9 `        Work closely with the California teams
# ]; ?  V5 n* x6 m! t8 a        Support chip tape out and bring up
5 P" Q, n3 d4 u: s. d, ^
* P/ H/ y  h+ y1 p& Z) y: t( oRequirement:
        8-10 yrs. experience  
        Knowledge of Verilog / System Verilog & Perl
& E6 J$ R0 i$ @  q        Has worked on complex project; experience with 802.11 is preferable
& G: \- N! T7 u$ O' i, l( ]        Can work independently - want him to take over MVE
: ^% D, \: b' g" n! ^9 y5 O. ~        Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus

ranica

ASIC Digital Verification Engineer
% W$ ^- @) Y; u0 f2 E( g公      司：A mobile chipset semiconductor company
8 A5 X9 h0 K% u0 v5 p工作地点：上海
- X" I# Z3 I1 c) i( E' o
/ v$ j2 p- g0 L6 y" d$ eResponsibilities:  
( S9 l4 k+ Q  _5 e( @7 J; G  Make verification plan for one module or whole chip.  
  Build up and maintain module-level and chip-level verification environment  
  Verify ASIC digital design based on case list, and output verification report.  
  Also responsible for lint checking and formal verification.  
$ k" T8 S8 I/ U: ]: f$ n
8 D; I2 S/ C2 iQualifications:  
' o4 y4 s+ r2 r" C. d& V' v4 U  Proficiency in logic verification.  
  Experience with Verilog logic design language.  
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
! o9 j3 }1 o, _1 h; j1 ]. `) `  Experience with C and C++ is a plus.  
  Experience with C_SHELL, TCL or PERL is a plus.  
" b( F1 [9 \- r; Y6 O9 u- B  Experience with UVM, OVM or VMM is a plus.  
  Good knowledge of SOC design is a plus.  
$ }% Y% x, F; G$ |& F9 m  Good knowledge of software design is a plus.  
& s% g  v# p7 Z* `" d: i5 `; F. H  Self-motivated and good team player.  
  MSEE or BSEE with 2+ years.

ranica

Staff Verification Engineer
6 \3 F+ H% c' W7 c5 |. v  U公      司：one famous IC company
工作地点：上海

Qualifications
MS in EE/CS/ME.  
Minimum of five  years experience.
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
2 |  g6 L5 ~3 k4 n9 VGood knowledge ddr protocol and computer system achitecture would be an added advantage.
Good knowledge of Perl and shell programming would be an added advantage.  
* A2 ?5 R; a9 i& f+ y
2 i. S' z' u; N: H) z1 cResponsibilities:
" v1 W( X. Q! _2 w1 _2 ?. V, l-Understanding the expected functionality of designs.
-Developing testing and regression plans.
' K$ \: F9 E% d8 j2 m& c-Designing and developing verification environment.
1 x1 _4 g" Z6 i$ @/ ^. z-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.
4 Q* b: e* @1 A! T- {
# J& @! _; T7 _2 g" XRequirements:
# }( Q5 h7 k7 A7 c  k! lExperience & Skill: 5 Years
0 Z$ H3 r6 j1 J* i-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
5 B8 E0 Q) U) m7 O2 A% C- x-Knowledge in ASIC/FPGA design process and verification tools.
/ A( p- V$ r) E-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
  R( _3 W. Z) B# u  ?0 v8 i-Familiar with C/C++.
; v! u( w! K6 t8 j* v% s- {-Knowledge of DDR protocol a plus.
-Independent and self-managing.

ranica

Staff Verification Engineer

' R0 A( ?# C- y公      司：one famous IC company
工作地点：上海

9 |: m( Z$ c& C' Z7 L- s0 b* I% qQualifications
MS in EE/CS/ME.  
Minimum of five  years experience.
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
! U& w7 O) ~/ t$ P' ^: LCandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
- {) R, }" _5 w' t3 b% ?/ ]Candidate should be familiar with industry standard ASIC design and verification tools and flow.
% x: L8 Z" C/ K8 q0 V2 CGood knowledge ddr protocol and computer system achitecture would be an added advantage.
+ Y6 s* L6 u% ^$ K5 BGood knowledge of Perl and shell programming would be an added advantage.  

Responsibilities:
! U+ {: j  a5 O* x+ k3 r( Z-Understanding the expected functionality of designs.
-Developing testing and regression plans.
-Designing and developing verification environment.
% x- w/ }4 \7 k- `  m4 M-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.

; e5 F% R7 K" D( l9 ~Requirements:
% l$ o2 t$ W; u% h. Z9 ], fExperience & Skill: 5 Years
. V  L! {5 u3 T1 i-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
-Familiar with C/C++.
% w9 p5 D+ P1 t4 A, `& i-Knowledge of DDR protocol a plus.
-Independent and self-managing.

ranica

Digital Design Engineer
7 x  W5 ?( U; L/ b. d; H. S+ B7 I6 V
公      司：A famous IC company
工作地点：上海

Duties
( S* a( n4 g: u5 r; ~Work with internal and external customers to understand product requirements.
8 Y8 p3 [" a8 B; P  i( uCreate critical silicon technologies to meet the product requirements.
5 T5 X' t: J3 O/ c& q2 D. G& jWork out critical design flows and methodologies to execute implementation flawlessly.
7 v( d2 r- _7 \$ K2 g6 ~Design and deliver final design through multiple stages like specification, micro-architecture, IP  development, RTL coding, verification, logic synthesis, DFT, timing convergence, as well as helping on physical implementation.
) m, L7 j( `0 S/ t4 c8 [& Z' {0 o3 EComplete full documentation.
  Y5 S, W; k2 m! bHelp and mentor junior engineers.

Job Requirements:  
Solid understanding of all SoC chip development stages is required.  
Hands-on Experience with complex SoC design flow is required.  
) \# x- Q( \% {' j0 C/ A" U, ^Hands-on Experience with RTL coding, simulation, verification is required.
1 b7 S- n3 x* D8 xExperience with DFT and timing tools is preferred.
Experience with ARM platform is preferred.
& M. K/ [4 f$ G8 H3 G  D6 oExperience with low power design flow is preferred.
Experience with system verilog is preferred.
Good organization and documentation abilities  
MS in Electrical Engineering and Computer Science with 4 years of experience in SoC design