there are several kinds of burn in method for IC .* x# ?5 O7 k& R+ m: y; Y
PCT and HCT and several combinations to test the DUT (device under test)8 V# P& j) \, A; g. k& M% b
The reason is the failure rate curve of "bath tub" 9 A4 L+ E/ y, m& v
So we do this to 'stress" the semiconductor to push to the failure condition that cause by ' N; `5 g( b# A9 o* Y# dsemiconductor degradation.8 ]5 I4 s4 U. f; T! Q! ?/ Q6 V; A/ J
I did this 16 years ago and I analyzed them to see the defect or failure mode. # [4 G% v' u& }. \& ZThe operation is only to ensure IC is working but most condition is cook IC wiithout active current in it.3 K9 y$ A. L9 z0 a6 D/ Z
Oh! those yang days!!
cannot totally agree with your teacher's word. 4 c: d% B7 \$ G) nI was test Eng but I experience lots TECH jobs including R&D . 8 i# {0 Y e4 i7 g$ A( _7 D% v7 l* h3 P% V$ J
I believe the only true way is :one day I'm EE the rest ofmy life I should be EE. 5 f4 }5 o# L4 H0 F+ r& f' d ( H% `6 B; T& |7 i! X2 g% XEE includes all the hardware software RF power,embedded tech,.....etc. $ L4 u! K6 ^1 M6 d+ G: \7 B) A, h / ]( d6 b! ^8 W& d. `: @2 }Do you think so?
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