何謂STI effect?

j5739792

I think what you are asking about is STI stress effect, which means the device performance being changed by stress from STI.   Generally, the STI stress impacts the MOSFET Vt (Ioff accordingly) & Ion by mobility degradation for NMOS (enhancement or degradation for PMOS, it depends) and species diffusion coefficient change.   For some process, PMOS Vt would even change more than 100mV for short channel device.   In BSIM4 SPICE model, the stress effect is modeled by mainly AA to gate edge dimension (along gate length direction).   This topic is also briefed inside BSIM4 user manual.   You can refer to it.