在鎖相迴路中如何決定迴路頻寬K呢？

kmchen3089

回復 #1 option318 的帖子
(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一
1 g5 }  E- o7 u/ [% J" ~否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump
pll ,且亦有unstability issue
& y( n/ l" M( x0 ?! Z4 z(see Charge-pump phase lock loops paper by Gardner
# h7 ?: H( j! }3 }) DIEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980)
(2) loop BW is related to jitter (or phase noise) ,and locking time
so you have to consider loop BW  from jitter & locking time  spec
(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq
(4) In my opinion ,gain margin is not considered in pll design