EDA戰雲密佈！RD戰力分析？

heavy91 · 發表於 2010-7-19 14:14:29

本帖最後由 heavy91 於 2010-7-19 02:26 PM 編輯

6/30/2010	SiS Adopts Cadence Technologies for Advanced SOC Designs
6/21/2010	Cadence Completes Acquisition of Denali
6/14/2010	Cadence Delivers Extensive Support for TSMC AMS Reference Flow 1.0 for 28-nm Process
6/14/2010 1 c4 {* O) @- H	Cadence Delivers TLM-Driven Design and Verification, 3D-IC Design and Integrated DFM Capabilities to TSMC Reference Flow 11.0
6/14/2010	Cadence Kick-Starts UVM Adoption with Open-Source Reference Flow Contribution to UVM World
6/11/2010	Cadence Announces Comprehensive SOI Design Hub
5/24/2010	Cadence and IBM Team to Develop Leading-Edge IP
5/24/2010	Rapid Bridge LiquidIP Now Available as Part of Cadence Open Integration Platform
5/20/2010	Computer Simulation Technology Announces Closer Cooperation with Cadence
5/14/2010	Cadence to Acquire Denali
5/7/2010	Cadence Accelerates SOC Realization, Reduces Costs with New Open Integration Platform
5/3/2010	VIA's Centaur Achieves Significant Benefits Using Cadence Virtuoso Space-Based Router at 65nm
4/26/2010	Cadence Debuts Verification Computing Platform
4/21/2010 ' O' n( h, U( V n( l3 y s8 Z	Cadence Contributes Technology to Boost Verification of Complex Mixed-Signal Chips
4/14/2010	HiSilicon Adopts Cadence Mixed-Signal and Low-Power Technologies
4/14/2010	LSI Adopts Broad Range of Cadence Mixed-Signal Technologies
4/14/2010	TSMC Expands Cadence Tool Support In Integrated Sign-Off Flow By Adding Synthesis, Place and Route, and RC Extraction
3/29/2010	Cadence Teams with AcAe to Accelerate Transition to Allegro PCB Products
3/24/2010	Renesas Cuts Design Time by Half on Large-Scale Consumer SOC by Using Cadence Encounter Technology
2/2/2010	austriamicrosystems Expands Reliance on Cadence Technology to Achieve Seamless Mixed-Signal SOC Designs
2/2/2010	Cadence EDI System 9.1 Addresses Productivity Crisis for Complex SOC Design
2/1/2010	Cadence Software Validated on STARC QA Database
1/27/2010	Renesas Adopts Cadence Virtuoso Technology for Mixed-Signal and Analog Design
1/25/2010	Cadence OVM SystemVerilog Solution Enables More Thorough Verification at Mitsubishi Electric
1/25/2010	NEC Electronics Adopts Cadence Encounter Digital Implementation System for 40-nm ASIC Designs

heavy91 · 發表於 2010-7-19 16:17:18

本帖最後由 heavy91 於 2010-7-19 04:27 PM 編輯

Mentor Announces Commercial Linux Platform for Freescale Processors Based on Power Architecture Technology	6/23/2010
Mentor Graphics Questa Functional Verification Platform Adopted by Mindtree	6/21/2010
Mentor Graphics Extends TSMC Reference Flow 11 with Support for ESL and Integrated Design and Manufacturing Closure	6/17/2010
Mentor Graphics' Olympus-SoC Place-and-Route System Now Supported By X-FAB	6/17/2010
Mentor Graphics Provides Comprehensive Verification Support in TSMC AMS Reference Flow 1.0	6/17/2010
Mentor Graphics Working with TSMC to Speed SOC Verification with Calibre Automatic Waivers	6/11/2010
Mentor Graphics Announces Calibre xACT 3D for Fast and Accurate Extraction Using 3D Field Solver Technology	6/8/2010
Mentor Graphics Underscores Support for OVM and Extends Support to UVM Across Multiple Products	6/7/2010
Mentor Graphics Introduces Precision Rad-Tolerant Product for Advanced Radiation Effects Mitigation	6/3/2010
Mentor Graphics 0-In Formal Version 3.0 Brings New Level of Automation to Formal Verification	6/1/2010
Mentor Graphics Releases 0-In CDC Version 3.0 to Support Verification Needs of Larger, More-Complex Designs	6/1/2010
Mentor Graphics Announces New FPGA Synthesis Innovation in Precision Synthesis 2010a Release	5/20/2010
Mentor Graphics and NetLogic Microsystems Establish Strategic Multi-Core Collaboration for Embedded Linux	5/19/2010
Valor Releases Major New Functionality In the vSure DFM Product	5/19/2010
Mentor Graphics Veloce Delivers 400X Acceleration for OVM Driven Verification	5/7/2010
Mentor Graphics Calibre InRoute Delivers True Manufacturing Sign-Off During Physical Design Closure	5/3/2010
Mentor Graphics and Lauterbach Collaborate On Hardware-Accelerated, Software Development and Debug Platform for SOC Verification	4/27/2010
Mentor Graphics Selected as a Key Freescale Commercial Linux Strategic Partner for QorIQ and PowerQUICC Processors	4/26/2010
Mentor Graphics Announces Multicore Solutions for Symmetric and Asymmetric Multiprocessing	4/22/2010
STMicroelectronics Adopts Mentor Graphics Veloce Emulation Platform for Its New Generation of Set-Top-Box Chip Sets	4/15/2010
Mentor Graphics Extends DO-254 Platform Offering with Enhanced HDL Coding Standards	4/14/2010
Mentor Graphics ReqTracer Automates Requirements Tracking and Reporting for Electronic Design Projects	4/5/2010
Mentor Graphics and Platform Computing Optimize Use of Veloce Emulation Systems as Shared Resources	3/30/2010
SMIC Bases DFM Sign-Off Strategy on Mentor Graphics Calibre Platform	3/30/2010
Mentor Graphics Calibre LFD Certifications at TSMC Now Include 28-nm Process Node with TSMC UDFM Engine	3/23/2010
The MathWorks and Mentor Graphics Outline Joint DO-254 Workflow for Model-Based Design	3/23/2010
Mentor Graphics Acquires Valor Computerized Systems	3/18/2010
Mentor Graphics to Extend Cooperation with STMicroelectronics for Advanced Chip-Development Design Solutions	3/16/2010
Mentor Graphics Adds AMBA 4 Verification IP to the Questa Multi-View Verification Components Library	3/10/2010
Mentor Graphics Introduces FloTHERM IC for Semiconductor Package Thermal Characterization and Design	2/25/2010
Dongbu HiTek Adopts Mentor Graphics Eldo for Optimized Cell Characterization Flow	2/23/2010
Mentor Graphics Eases Android Development with Support of Inflexion Graphical User Interface on the Zoom OMAP36x-III Mobile Development Platform	2/15/2010
Mentor Graphics Enhances Signal and Power Integrity Solution with Full-Wave 3D Analysis	2/3/2010
Agnisys Announces Support for OVM Register Package in IDesignSpec	2/1/2010
Mentor Graphics Catapult C Adds SystemC Synthesis and Expands Full-Chip Capabilities	1/25/2010

heavy91 · 發表於 2010-7-19 16:30:03

本帖最後由 heavy91 於 2010-7-19 04:34 PM 編輯

SVTC Technologies Selects Synopsys' Manufacturing Tools to Accelerate Time to Commercialization	7/14/2010
Open-Silicon Integrates 50 DesignWare Interface and Analog IP Products with 100% Silicon Success	7/7/2010
ARM, IBM, Samsung, GlobalFoundries and Synopsys Announce Delivery of 32-/ 28-nm HKMG Vertically Optimized Design Platform	6/17/2010 3 ~' F8 C! a" w! \) `6 m: r9 }
PrimeTime 2010 Scales Timing Analysis Beyond 500 Million Instances	6/17/2010
Synopsys Delivers Optimized Lynx Design System for Common Platform 32/28-nm Technology	6/17/2010 + i8 G/ `% V; I9 E
Synopsys Unveils Galaxy Characterization Solution for Standard Cells, Complex Macros and Memories	6/17/2010
Synopsys Unveils StarRC Custom 3D Extraction Delivering 20X Speedup	6/17/2010
Synopsys Delivers Comprehensive Custom Design Solution for TSMC Analog/ Mixed-Signal Reference Flow 1.0 " j+ [5 c& I6 f1 h	6/11/2010 3 J0 S1 n$ O8 J/ S) x% L1 P& x
Synopsys to Acquire Virage Logic - t& w) d& {8 {	6/11/2010 , z0 l8 H1 ~. w. P! Z
Synopsys and IEEE-ISTO Launch Technical Advisory Board to Evolve Interconnect Modeling Standard 4 u$ ^, s" w+ e- C" c: c	6/7/2010 ; C3 [, A* x- N. J0 J& `
Synopsys Announces Synphony HLS Support for Xilinx Virtex-6 FPGAs 0 }6 O1 T. P/ O% {; O$ @6 }	6/4/2010 4 Q& o D5 y1 P) u0 ]8 r% q
Synopsys Press Publishes "The Ten Commandments for Effective Standards" 6 o+ A5 Q9 D. M6 o: E	6/4/2010 , D% U5 x; n- _; p H* Z
Synopsys Collaborates with SMIC to Deliver USB Logo-Certified DesignWare USB 2.0 nanoPHY in SMIC's 65-nm LL Process Technology ' C7 c. J. D0 b: z* I& z	5/13/2010 , h* P& b2 ?) L( A7 K X1 H x% W
Latest Synopsys IC Compiler Release Delivers More than 2X Speed-Up, Enhanced In-Design Technology and Production Support for 28/32nm 6 Z. u2 X& o4 \9 s$ m, B	5/7/2010 / V+ P! Q0 a7 {% y6 ^
Synopsys Unveils Ethernet Controller IP with New Audio Video Bridging Feature % w8 {0 K! r" A; P D	5/7/2010 ! a0 k9 U, _6 v$ ?# N
Synopsys Launches Industrys First MIPI DigRF v4 IP ! H( m9 @! i7 W1 ^0 P+ k" @: @	5/3/2010 0 E* ^( a. G/ s5 A
New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces 7 m; O& f$ _' f4 @	4/28/2010 v1 X% z' b' E n! y6 \
Synopsys Announces Support for Actel's New SmartFusion Intelligent Mixed-Signal FPGAs - k7 }; }5 d9 K S7 ~2 \	4/22/2010 ( `/ f- c" \& e
Synopsys Introduces the HAPS-60 Series of Rapid Prototyping Systems 0 W: }' J d# \|. A( A' i# \|	4/19/2010 - r7 ~- V/ M( q' y9 Z. l8 N4 X
Synopsys Expands IP OEM Partner Program with Two New Members 0 O2 {3 H7 f7 s' s) V	4/14/2010 # ^* r9 C; `& E, o0 }
Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards In a Single PHY / U# Y: W% i2 B3 F0 w$ m) E	4/7/2010 " @. S1 q+ O' p' c# p
Synopsys' DesignWare SuperSpeed USB 3.0 IP Receives USB-IF Certification + F. h% ?4 Z, N. }% S5 S	4/5/2010 ! r0 C( _. [" G& I+ t
SiliconBlue Selects Synopsys as FPGA Synthesis Partner for Its iCE65 mobileFPGA Family 0 g1 N w {# C4 E	4/1/2010 & Q% K5 C# C. ?* x
Synopsys Galaxy Implementation Platform Enables First-pass Silicon Success on Infineon's 40-nm X-GOLD 626 Wireless Product . W Y5 F, S0 m2 b+ e3 \	3/30/2010 5 @; B7 ~3 ^3 k/ ^! k. Y
Design Compiler 2010 Doubles Productivity of Synthesis and Place-and-Route ; w- ^) g" \' I* S	3/29/2010 ) U: a% U8 y! L! c; X
Nationz Technologies Achieves First-Pass Silicon Success with CustomSim Mixed-Signal and VCS Functional Verification Solutions 3 y/ T: P. K% D& y	3/23/2010 9 X& J' ?( o# N0 r: P
Renesas Technology Adopts Synopsys Proteus OPC for 28-nm Development 8 S( U* m& O/ x& f$ [! ?& u1 G1 q2 t7 R	3/23/2010 " \; A, l/ F- }1 f" z8 G! P
Synopsys Completes Acquisition of CoWare 8 m: U0 D+ S% j: `9 \|) O: U	3/23/2010 6 ]* {; {6 b1 u' r. z
IMEC and Synopsys Collaborate on 3D Stacked IC Development ( `# F# t2 r/ c8 \|2 H/ a	3/10/2010 6 }' h0 a6 m% \|
Synopsys Galaxy Custom Designer Accelerates Analog/ Mixed-Signal Engineering Productivity with Built-in DRC Visualization and Correction , n3 F0 b5 N# M9 I) E	3/10/2010 : i- ^9 E9 M8 R( s( `; \|# {
Yamaha Tapes Out Graphics Chip with Synopsys Design Compiler Graphical . B+ Y" F- Y* g) p+ E	2/9/2010 2 U1 f1 e( q! Q# d
APAC IC Adopts Synopsys Galaxy Custom Designer Solution for Analog/ Mixed-Signal IC Design Services 9 w# ~9 Z# S& K* Z, h" d7 ~	2/8/2010 8 J; Q2 p7 x% Q w- D9 V
Synopsys to Acquire CoWare ) E. b: H0 p; p% K( u	2/8/2010 , g4 p$ a8 c8 ]5 }0 P: K
Synopsys Acquires VaST Systems Technology 9 ?2 w# D; r" p	2/3/2010 * y6 \0 D! v7 T7 @- s
Synopsys Expands DesignWare IP Portfolio with MIPI IP Solutions + i6 Y1 t! N r4 W$ z	1/25/2010 v4 g: O% E' o: t! ]& s6 \! u
Synopsys Launches DesignWare HDMI 1.4 Tx/Rx Controller and PHY IP Solutions for 40-nm Process Technologies * }/ {2 Z5 N* f	1/25/2010 4 A8 u: S/ E0 I2 l
Toshiba Information Systems Standardizes on VMM-LP Low-Power Verification Methodology + L6 g0 r) B: K) h& a+ }	1/25/2010 3 h# v. f2 \|) Y0 P' F5 s! Y
Synopsys Announces DesignWare Protocol Analyzer for Verification of SuperSpeed USB 3.0-based Designs ! D, P) ]; A% K' c- e	1/13/2010 / g% d. [; m7 y7 }, x# x$ k+ Q
Synopsys Introduces SystemC TLM-2.0 SuperSpeed USB 3.0 Models 1 U( e3 K; S7 c" x0 g# y	1/12/2010 0 U i1 ]8 S4 q; ?; x
Synopsys Multicore Technology Speeds Timing Sign-Off by 2X : T- c; J4 P% {- ?; H3 c: y& H	1/11/2010 9 X$ }3 ~$ W' @; o5 ~

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EDA戰雲密佈！RD戰力分析？

2010上半年Cadence重點新聞彙整

2010上半年Mentor Graphics重點新聞彙整

2010上半年Synopsys重點新聞彙整