IEC 公布 DesignVision 獎入圍名單

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一年過去囉！與去年比較起來，差別多大？誰勝誰敗呢？:o
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! W' g+ b4 Y/ T; I8 m' r  RAward recipients were selected in eight categories.
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. S, r1 C7 B: G' r$ h* d+ z+ D% RASIC and IC Design Tools

• Cadence Design Systems, Inc. — Cadence Litho Electrical Analyzer

Design Verification Tools

• Mentor Graphics and Cadence Design Systems, Inc. — Open Verification Methodology

Interconnect Technologies and Components

• Amphenol TCS — XCede

Semiconductors and ICs

• Altera Corporation — Stratix III FPGA

Semiconductors and ICs (IP)

• Rambus — The XDRTM Memory Architecture

Structured/Platform ASIC, FPGA, and PLD Design Tools

• Lattice Semiconductor — LatticeXP2 FPGA Family

System-Level Design Tools

• FuturePlus Systems, Corp. — FS5000 Jitterlyzer

Test and Measurement Equipment

• Agilent Technologies — Agilent N6705A DC Power Analyzer

Congratulation to the 2008 DesignVision Award Finalists
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& n. H  \# z( Y1 L. K5 G+ ZWinners will be announced during a special DesignVision ceremony taking place at 12 noon on Tuesday, February 5 in the Theater. DesignVision Awards recognize technologies, applications, products, and services judged to be the most unique and beneficial to the industry. DesignVision Awards also honor corporations and individuals for innovative contributions and developments that have proven important to society. A

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• Cadence Design Systems — Cadence Litho Electrical Analyzer
• GiDEL — PROCStar II
• Sequence Design — PowerTheater-Explorer

Design Verification Tools

• EVE — Zebu-XXL
• Mentor Graphics and Cadence Design Systems — Open Verification Methodology
• Synplicity — TotalRecall Full Visibility Technology

Interconnect Technologies and Components

• Amphenol TCS — XCede
• Cinch Connectors — Cinch® iQ[size=-1]TM Hybrid Interconnect
• Sigrity — OptimizePI

Semiconductors and ICs

• Altera Corporation — Stratix III FPGA
• Chip Estimate — ChipEstimate.com and IP Concierge
• Gennum Corporation — 3 Gb/s Optical Module
• Lattice Semiconductor — LatticeXP2 FPGA Family

Semiconductors and ICs (IP)

• ARC International — ARC Video Subsystems
• Rambus — The XDR[size=-1]TM Memory Architecture
• Xilinx — Xilinx® MOST® NIC LogiCORE[size=-1]TM IP Solution

Structured/Platform ASIC, FPGA, and PLD Design Tools

• Altera Corporation — Quartus II v7.1 Software with Enhanced SOPC Builder
• Lattice Semiconductor — LatticeXP2 FPGA Family
• Xilinx — Integrated Software Environment (ISE?? 9.1i

System-Level Design Tools

• Carbon Design Systems — Carbon Model Studio
• FuturePlus Systems — FS5000 Jitterlyzer
• Synplicity — Synplify DSP ASIC Edition

Test and Measurement Equipment

• Agilent Technologies — Agilent N6705A DC Power Analyzer
• ASA Corp. — M1 Oscilloscope Tools v5
• SyntheSys Research — BERTScope Phase Locked Loop Analyzer

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記憶體架構榮獲備受尊崇之國際工程協會（IEC）獎項

(台北訊，2008 年 2 月 21日) 專精於高速記憶體架構技術的全球技術授權領導公司Rambus Inc.（納斯達克股票代碼：RMBS），宣佈國際工程協會（International Engineering Consortium，IEC）評選Rambus的XDR™記憶體架構為2008年半導體與積體電路（智慧財產權）類別的DesignVision大獎得主。國際工程協會DesignVision大獎評賞獎勵業界最獨特、受益性最高的技術、應用、產品和服務。
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5 P. b- W0 R4 ^5 B6 F國際工程協會執行副總裁Roger Plummer評論，「今年的獲獎者是當今業界最高水準的創新典範。我們熱誠祝賀Rambus，該公司的XDR記憶體架構在DesignCon 2008展會上獲得2008年DesignVision大獎。」
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! h# e' F2 E9 ]. \, D& u0 vRambus資深工程副總裁Kevin Donnelly表示，「我們感到十分自豪，能夠推動最先進的創新記憶體架構的發展；我們也為獲得IEC的肯定而感到榮耀。XDR架構是一個全面的記憶體系統解決方案，能夠以最少的零件實現極快的速度，因此最適合運算和消費性電子應用。」

* s! R. _) ~! \2 ?1 D( eRambus最近宣佈，東芝公司為其下一代高傳真電視晶片(HDTV)取得了XDR記憶體架構的授權。另外，奇夢達（Qimonda）的首批XDR DRAM樣品已經開始出貨，爾必達（Elpida）的4.8GHz XDR記憶體也已出貨，該記憶體是全球量產中最快的動態隨機存取記憶體產品。
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XDR記憶體架構賦予以下核心元件獲得突破性的效能：
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nXDR DRAM：這是一個高速記憶體積體電路，它利用4.0GHz資料率的高速介面來提高標準CMOS 動態隨機存取記憶體核心的性能，單獨一顆零件就能提供高達8GB/s的頻寬。
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nXIO控制器輸入輸出單元能提供與DRAM相同的高速信號功能，而且增加改進的FlexPhase™技術，使得時序能夠達到最佳化，不必進行[佈局繞線的等長配置]（trace length matching）。
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8 Z3 L& `/ u6 \' p9 C0 o9 gnXMC記憶體控制器：這是一個可完全邏輯合成的記憶體控制器，這款優化產品能夠充分利用動態點對點（Dynamic Point-to-Point）的優勢，提供後續容量擴展能力的創新技術，同時能夠帶來點對點信號的信號完整性優勢。
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nXCG時鐘發生器為系統時鐘提供四個可程式選擇的輸出，能夠做好保障，滿足XIO和XDR DRAM裝置的時脈需求。

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Altera宣布其Stratix III FPGA榮獲國際電工委員會(IEC)半導體和IC類的創意設計獎(DesignVision Award)。該產品獨特的創新架構獲得IEC青睞，在此架構下，Altera推出性能好而功率消耗低的高階FPGA。獲獎元件的傑出特點在於其DDR3記憶體介面，記憶體速率超過1067Mbit/s。該公司在聖塔克拉拉會議中心舉行的DesignCon 2008頒獎儀式上獲頒這一創意設計獎。  
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自2005年，IEC的創意設計獎主要頒發給業界最獨特、最有效益的技術、應用、產品和服務等。創意設計獎提名從創新性、獨創性、市場影響、用戶受益情況及給社會帶來的價值作為審核標準。  

Altera Stratix III FPGA最關鍵的架構創新之處在於其低功率消耗特性，包括可選內部核心電壓和可編程功率消耗技術。利用上述創新技術，和前一代高階FPGA相比，Altera元件的整體功率消耗降低50%。該產品具備性能好、功率消耗低的I/O及優異的訊號完整性。創新技術使Stratix III FPGA的DDR3記憶體介面速率超過1067Mbit/s，和競爭FPGA解決方案相比，記憶體性能高出33%。

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SANTA CLARA, Calif., 04 Feb 2009

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that the ChipEstimate.com IP ecosystem has been recognized with a DesignVision Award by the International Engineering Consortium (IEC). DesignVision Awards recognize technologies, applications, products, and solutions judged to be the most unique and beneficial to the semiconductor industry.
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* p# j, P% h: C# S"We are honored to receive this recognition of the value the ChipEstimate.com portal brings to the electronics industry," said Adam Traidman, group marketing director, Chip Planning Solutions Organization at Cadence. "The honor is shared with the over 200 IP suppliers and foundries who work together to accelerate our mutual customers' design success."

"The IEC's DesignVision Awards recognize top contributions to the design engineering industry. We're pleased to recognize Cadence Design Systems as a DesignVision Awards Winner for its ChipEstimate.com IP ecosystem," commented IEC Executive President Roger Plummer.

The ChipEstimate.com chip planning portal is an ecosystem comprised of over 200 of the world's largest IP suppliers and foundries. These companies all share in the common vision of helping the worldwide electronics design community achieve greater profitability and success. To date, a diverse global audience of over 20,000 users has joined the ChipEstimate.com community and has collectively performed over 80,000 chip estimations. ChipEstimate.com is a property of Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation.