標題: free DRAM controller~~~ MIG [打印本頁] 作者: tommywgt 時間: 2007-7-24 12:23 PM 標題: free DRAM controller~~~ MIG Software Support + \' ?+ f- Z3 v/ _2 t. K0 u- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i. : O* n7 C2 u# ^0 m6 O- U" q: K9 l4 p6 D4 Y1 r5 W4 h$ s3 i& X
Platform Support ' I% ~( G! I; U0 R. |2 \( R- Microsoft Windows XP (32 bit) & ]# R7 F$ `& U2 Z, E% w/ w 7 w8 k/ t8 g% L) t3 J1 ~$ a+ eDevice Support / B# B5 ^$ C5 U0 U, N/ N3 A3 x
- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported. : ? B! i8 h7 K$ d 5 Y% r9 X9 c( d4 `- [ e( t9 vNew Features 7 {! }6 p! |7 V( {8 x. K$ g
General New Features and Changes + G% |' x+ K% v, k; R7 O- Supports "Create New Memory Part" for all the designs. . D& x G5 ~. Z( \, H& n
- DDR and DDR2 SDRAM designs for Spartan-3A. D' U3 ^+ A! Q" `' Q1 _7 |
- DDR SDRAM is supported for Virtex-5. 5 e1 Y* f! O! G4 R1 k8 I5 D2 r/ d
- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM. 9 x) i2 A. H9 J! G7 t5 e+ t
- MIG now pops up the design notes specific to the generated design. # B& G" M9 H& v9 T3 n0 \9 h9 ]% z
- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs. 6 P: P$ B, {$ a0 d4 @2 K4 w- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes. ! t* [- s: z3 x& ^' J$ R- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2. 7 Y9 A6 o0 x4 z- W
- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A. # a4 |$ H2 T! v$ ?! p# l* I
- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST". ' K" d* ~8 j: |: D6 u; _, I- I
- Default setting "DCI for Address and Control " is changed to "unChecked". % Y1 [. ?9 a% _% T, }- Frequency slider is changed to editable box in the GUI. 8 C9 [* E; W3 s3 J- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names. b/ u( Q$ E6 b7 F6 [4 J) \5 Q
- Removed console window when running MIG through CORE Generator. : V7 k0 c' ]( o' Q6 `, m; z
- WASSO table (Set Advanced Options) accepts only numeric characters. " ^) U# q# v- h+ i: v# n- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32. - l! M( p8 O8 c& H+ j4 W4 w+ D- V- Provided web links for all XAPPs in the docs folder of the designs. 4 Y8 |( e) b7 R9 {5 T* K- Provided link to Data Sheet instead of Log Sheet in the output window. 7 E; O* a4 \1 w. N' G
- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window. 5 n5 \% ^3 E; o3 P# s
- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank. * l. R6 l' O" u8 o: T
- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition. . F) C9 E' L/ [7 k( t1 c! z
# M# j: p# R0 K# ?% c
Virtex-5 New Features and Changes 5 i( z+ b# {, G( GDDR2 SDRAM 2 C2 {% V6 w+ m& Y2 P8 r- New controller with several high-performance features. All the features are described in detail in the Application Notes. $ V7 c9 S4 T! I2 e4 A3 [7 C, I+ A" R- Enhanced data calibration algorithms for higher reliability. & }) c% Q, ]8 Z+ e2 l1 Z! R2 f2 p- Bank Management feature is supported. % B/ O, K3 W6 V. F; ?7 k1 W) \3 @' w- Supports VHDL. # {5 }8 U$ T- B/ g+ @- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear. 1 `8 @7 t9 n( z' l* W
- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus. 0 o( y- z6 }: b0 J" V+ f- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions. 3 Z- ]1 L+ E4 X! [5 z* b7 J+ f
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. / ?, x: R& X4 ]" V8 V* C$ Yb. WASSO is applied to all the memory interface signals. 2 {7 k7 I0 R' e$ n3 s
c. Signals such as "Error" outputs are not part of the WASSO count. 6 i7 y4 ?: q: X& _4 J2 p) _1 E, v7 u8 ?. ~" J _
DDR SDRAM 9 k# w& ^0 v; G/ |) B- This is a new design for MIG. Supports Verilog and VHDL. # M# y" r' [ S I* u4 K
- Bank Management feature is supported. % o* @* v. m- U- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear. - y7 C9 e; c, y 9 ^4 K/ s$ Q8 Z) P! E* ZQDRII SRAM ( f2 N, r- z* _5 i7 _- p/ X- Added support for VHDL. # W# V4 Y* i6 U. r2 J! Q( h- Added support for 72-bit designs. ( S( M' R( f. G* Z
- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay. ) U( I) K+ Q) Z' c6 v3 _; g E4 \
- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6 % `, a: R2 e& u4 K2 D0 K
- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons. - D4 Z3 g9 S Y; J8 \6 T: M2 C- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 6 |, a$ L f4 K! Q3 ?* E. d
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. , z* g8 n$ f, q. u/ b. L4 r0 g( Db. WASSO is applied to the output signals only. 3 n+ E1 X+ X" J% O/ ^1 l( i) ]' e
, ^* g3 w6 J `9 i6 D8 lVirtex-4 New Features and Changes ! y8 {6 J7 w9 c% e
DDR2 SDRAM Direct Clocking 8 |1 ^' w# c( ?( r" F- f
- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design. / E6 j3 o u: z: j$ q8 F
- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins. 2 g% l$ j9 c) u9 @
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 3 z) }' ]% L7 B: r
- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options. + f+ M" W- Y' o4 _
- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers. D8 C/ u: K1 v( r8 f- Removed all TIGs in UCF. The reset signal is now registered in every module. , o9 X4 h$ T7 m- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. ; c5 v) ]9 ?1 Q! T- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. , X c% ?4 ~ J/ k1 K+ v
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. * Z& t, X ?) ~1 M/ g& y1 p
- Replaced `defines with localparams for Verilog. * m# a. Z3 Z# v F6 Q* l& O
- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. ! b5 F" B& m) t% n! _) O' ]; E* W
- Several state machines now use "One-Hot Encoding". 7 y! U% i5 z! [! [7 L& j- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. 5 }$ \8 G, Z/ ~6 R8 w. R: y9 F
- Signal INIT_DONE is brought to top module. 4 B$ ` W. h" x- Removed the UniSim primitive components declaration from VHDL modules. " y. Q" l4 Q4 {$ \* C6 h6 R- We now support all multiples of 8-bit data widths even for x16 memory devices. ! z# B" b3 t) c1 ]% @! i; c
- We support memory devices of speed grades -3 and -667. " p: G1 `& z6 }: J3 |, t7 z& k8 s
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. ' D( S0 U8 c8 ]% }% ^' C
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 7 |5 S& M7 D Xb. WASSO is applied to all the memory interface signals. 5 _- @0 D0 S" u1 s6 g
c. Signals such as "Error" outputs are not part of the WASSO count. # g5 n- w& ^# H) [& O/ h$ I$ W( H. v* e% p+ t y! ]) K+ _
DDR2 SDRAM SERDES Clocking / }& |) f# L( @- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note. * t0 U" R, W( `, h: X5 e1 m- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 5 I! T+ \7 g, P# m
- Support for ODT. W. [$ y, ?- ]! `
- DQS# Enable is selectable from GUI through Mode registers. 9 K$ Y0 y9 p8 I$ ~2 C8 A
- Removed all TIGs in UCF. The reset signal is now registered in every module. 1 M- H2 k. i, u0 c! g
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. - `; e! j u' H1 C {: A$ C- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. 9 c- l K" c5 Y) m; I0 F
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. . L9 K) @* @. ]6 h6 T* U
- Replaced `defines with localparams for Verilog. ( v9 s: U. W; `4 y/ B+ f% W
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. 6 V% t1 b# T/ p: q* t
- Removed the UniSim primitive components declaration from VHDL modules. / F+ z" t2 F6 j4 |: A: o
- We now support all multiples of 8-bit data widths even for x16 memory devices. % J, m7 r6 Z" S* R- Signal INIT_COMPLETE is brought to top module. ' l; Y4 T: a" z7 Z- Z# e! g2 ]
- Memory devices of speed grades -5E and -40E are now supported. # L) [2 s2 p, m l0 l& x- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 9 o9 V+ J# C5 O$ va. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 4 ]! `0 `' W+ e# g3 G. u: e2 ?b. WASSO is applied to all the memory interface signals. $ L) H2 n! L$ r6 l, d3 O" Q1 tc. Signals such as "Error" outputs are not part of the WASSO count. $ j7 P' l! J% b$ a0 z& u
/ [8 j2 t9 d1 \' P2 n5 ]7 HDDR SDRAM 2 z0 B3 o% ]) H1 }& ~1 m
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. ) Q" {: E6 F0 q4 k8 M0 e' F
- Removed all TIGs in UCF. The reset signal is now registered in every module. * K' b) |6 H7 E- R7 W- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. / v: P! Q( ]$ Z7 [* n
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. % L5 t* `5 w3 n/ F% W5 \- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. $ f: X v: W/ c
- Replaced `defines with localparams for Verilog. w, g( F' t) G. X& e; E" K- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. : K0 _; ?! b* [$ o2 \0 q- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. ( X# U* Z2 Y) {! f+ e- Removed the UniSim primitive components declaration from VHDL modules. # j& M! W; \# Y- We now support all multiples of 8-bit data widths even for x16 memory devices. - ^2 I q# t4 @
- The signal "init_done" is now a port in the top module. ! Z2 N4 G! \4 \4 ^- J- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 0 n* V/ K/ v' N! ^2 _
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 6 r/ v3 s! V& _! B
b. WASSO is applied to all the memory interface signals. 8 o+ |8 y% D, a. n
c. Signals such as "Error" outputs are not part of the WASSO count. + @" \; L9 H9 V" ^9 B$ S3 V$ d6 Q* r! f5 K
RLDRAM II 6 L0 ^3 d+ q+ o$ d5 r; V2 H8 q N
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 5 m' C% V4 v9 Z* J9 b$ K- Removed all TIGs in UCF. The reset signal is now registered in every module. 1 W' v' N, h7 T) W- The design now uses CLK0, instead of CLK50 and div16clk. 1 z: m7 n# J4 X: K8 W3 J4 ` R
- CLK200 is changed to differential clocks in mem_interface_top module (Design top). - }8 R" v8 N' ~8 w6 G: u
- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal. 7 m; b4 O# V3 Q( \. W- Removed unused parameters from the parameter file. # \5 j5 l& p4 T' w; U+ B" v2 M) G- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. ' X. W* I2 \4 C) k3 @4 T
- Replaced `defines with localparams for Verilog. 1 b7 W2 I2 B4 S! [/ R% ?
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. d* f) {3 J' w. c9 W
- Removed the UniSim primitive components declaration from VHDL modules. 3 k2 |: M% _% d, }
- The signal "INIT_DONE" is now a port in the top module. 2 v0 X8 ^6 Y* P: X8 ^- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8. 1 L5 X7 F* G: n: D- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets. * s* g, Q5 k( @+ ^8 z" [- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file. 1 ~! ~! @7 z U$ E- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 2 u, s7 Q* U8 Ma. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. ( w2 J( a* Z* }4 V) c+ n9 `( J9 v3 zb. WASSO count is applied on output signals only for SIO memory types. . \+ _& m0 t. _0 ~1 ?+ X9 Zc. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool. 2 b9 q. O5 \+ v) r& p( B% P # \. G/ S' e& C, M2 M- a @' ?QDRII SRAM 6 r( V+ R$ v8 Q" g7 \* b% d7 q
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. : h9 w, l0 P" s8 Q1 c
- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic. - B% {. ]. F; |
- Supports generation of designs with out DCM. 1 l: C7 K8 `2 v) Q6 K! ]$ v: M- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC. 0 s9 {, v" { |2 _7 ~+ T
- Removed all TIGs in UCF. The reset signal is now registered in every module. 5 m3 b& l7 s8 |5 d+ z. u0 K- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 8 _2 f! |% H& u0 l4 i# _- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. & N" s- N2 a- r8 Y& z! R
- Replaced `defines with localparams for Verilog. : V. z+ m( _; W7 n6 t- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. $ C+ U, {* R) b4 G3 D
- Removed the UniSim primitive components declaration from VHDL modules. & c# w, t5 E! g( e- The signal "DLY_CAL_DONE" is now a port in the top module. ! g& `3 d4 ?8 ^, K) r/ u- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. 9 C( Z' S' R3 f; g3 Q/ q- Added support for DDR Byte writes. / S C8 c4 i9 g% E5 u* h- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. G, R6 T, N% e% Ja. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. + Y6 n2 j0 `, m1 E
b. WASSO is applied to the output signals only. ! e1 r5 y! H' n( x: C
c. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool. 1 t A' K0 o9 I& y1 q j6 C S0 ^% y+ G
DDRII SRAM . U4 s% X" }$ @' w7 c" p0 K$ [
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. & d: o, i R9 }' o4 G% r
- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic. % [+ O- Z" b; X/ k" Q- Supports generation of designs with out DCM. : o" o- }0 w, b9 T! ]- Part CY7C1526V18-250BZC has been removed from Memory Parts list. 8 K! ~0 k, Y0 D& Z2 g
- Removed all TIGs in UCF. The reset signal is now registered in every module. " o+ M) E8 B# `/ u: G% m! C2 `
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. ; ~+ c8 D( n$ ]6 A: P- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. 9 ^0 \ T1 t+ i2 }/ l- Replaced `defines with localparams for Verilog. 6 Y; \; F1 g6 v) ^/ r
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. " b7 w4 _5 x1 i- N+ a6 I- Removed the UniSim primitive components declaration from VHDL modules. ) N' c: X" n" o* H& S5 {/ S- The signal "DLY_CAL_DONE" is now a port in the top module. " W4 C. B) s3 w+ B+ Y, J- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. / ^/ P6 S9 I* \8 v3 c! A
- Added support for DDR Byte writes. 6 R! H5 s5 T% ~8 [) `, h9 u" z& K$ u
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. , C& _5 _" R4 q h" a
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 5 d+ y: P( @7 \/ }( Y8 X$ Z
b. WASSO is applied to all the memory interface signals. 7 N+ C. t3 d. C
c. Signals such as "Error" outputs are included in WASSO count.作者: tommywgt 時間: 2007-7-24 12:28 PM
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