, S) u0 @ |6 |% _第一個就是 Device model的準確性 ) D! G c8 a- ZDevice Model不準 RD就得為了模擬上明明進spec / ], S% H, l: Y, @5 w* x' b9 Phardware 回來卻 飄掉的問題 不斷的改版 ; `) F) X5 J& l. u! `不只是 一直浪費研發人員的時間 也把公司產品推上量產的時間不斷延後.8 @+ Q+ Y: F9 c" }# _/ {
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第二個就是 PM與Marketing 必須要制定合理的銷售策略 $ i O$ V- W" D, m9 X正確的看出 未來的趨勢 7 R; \' v9 z. N趨勢看不正確 最後就只能 叫RD 作一大堆option在同一個Mask裡面 0 {4 h6 Q, L: o7 a其實 越多產品 combine 在一起 乍看之下 好像一網打盡 \6 C5 g! x7 [3 r T7 w% j- @; R
實質上 卻把 每一種產品的競爭力 都打趴了 (Die Size增加, IC在市場存活時間減少)作者: jacky002 時間: 2008-1-30 11:09 PM 標題: 回復 3# 的帖子 對第二個部分 . ]5 f: d' s, n( H G=================================================================================& M0 f0 R- p g+ o. D& \( t
第二個就是 PM與Marketing 必須要制定合理的銷售策略" H5 e: w, g, w0 n. r. J% c: S
正確的看出 未來的趨勢' n$ `- l6 z2 r9 c2 [
趨勢看不正確 最後就只能 叫RD 作一大堆option在同一個Mask裡面 & k/ U; i* t2 m3 J; I; `* T# b其實 越多產品 combine 在一起 乍看之下 好像一網打盡- i6 d1 R2 ]$ C! f8 j
實質上 卻把 每一種產品的競爭力 都打趴了 (Die Size增加, IC在市場存活時間減少) 0 R O* F/ s4 a- k/ E3 P' I=================================================================================# X" @7 Z8 \2 F, Z( u* r
所言確實，但這也就是PM與Marketing難為的地方。- n& z9 Q$ j* s3 ?3 M% I
為了要能保證產品一定要能有賣點又不會被顧客說規格開得不漂亮， 0 N& e6 O F. q其實真的也是普遍的現象。 + v# c8 K4 T; }# [$ J) I: O1 P0 K4 q試問哪個PM與Marketing在開規格只是關起門來，自己說了算?5 X" r2 v6 T) {' F9 r. U- \
我相信一定是收集市場與顧客的資料，然後才敢將產品規格訂下來。 U0 G% h" ~: X2 I t雖然我正在往PM與Marketing的方向邁進，但身為RD的我，& _! E; o& v, f' b: ^/ ~. p
其實這兩種不同的角色我都能體會。 & {# Q7 T) O9 ?3 w. g是否大家有不同的看法，可以一起來討論，交換意見也不錯。作者: ranica 時間: 2011-8-19 02:51 PM
招聘公司：A famous IC company 1 ^# q2 O; G y1 a B5 E招聘岗位：Project Leader4 Q' J& k0 y9 e$ R4 {+ l
工作地点：Shanghai1 b' H/ K! U: P& r3 s3 G% s1 T
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岗位描述：; y' z5 L! J3 Q- Q0 q" a% Y, N, t
Job Description XX is looking for motivated engineers who can show they are capable of learning to work on complex IC designs, to the highest quality and in record time. XX’s engineers have expertise in delivering the lowest power solutions in advanced technologies, covering technologies down to 28nm, design sizes in excess of 300mm2, and applications from mobiles, to graphics and network IC's. XX works with leading EDA and IP companies, and its expertise has been recognised through its alliance partnerships with SMIC and TSMC. Depending on experience, key responsibilities will involve some of the following: · Development and optimisation of high performance and low power Soc physical implementation methodology · Working with European engineers to do block level and full chip floor planning, timing and power analysis, and P&R · Design consulting in customer's offices on physical implementation tasks · Interfacing with foundry and IP providers on IP imports and test definition.' l1 C( @' p: ^
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职位要求：4 L) Z- o$ B, f2 m8 E5 [/ K9 n) Y& b
Desired Skills and Experience Some experience in physical design engineering coupled with a good degree and a desire to be at the leading edge of new technologies. The successful applicants will have exposure to at least some of the following areas: · Digital Soc chip design and implementation · Design automation and analysis using scripting languages, particular Tcl and Perl · Design Flows and the EDA tools, in particular tools from Magma, Mentor and Synopsys. Experience with tools from Apache and Azuro would be an advantage · Sign-off methodology and EDA tools for STA, Noise, Power, etc. · Structured design styles involving placed gates · ATPG tools and methodologies.