Chip123 科技應用創新平台

標題: EDA戰雲密佈！RD戰力分析？ [打印本頁]

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作者: chip123    時間: 2006-7-25 03:41 PM
標題: EDA戰雲密佈！RD戰力分析？
投票者如能說出：為何你認為這家比較強，可能對大家幫助更大!? 和這三家廠商相關的人士，請不要投票干擾喔！
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全球3大EDA廠台灣研發中心全數就位
明導3Q將設立研發中心 益華編制將倍增　新思龍頭地位備受挑戰
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（電子時報記者宋丁儀╱台北） 2006/07/20   
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台灣再度成為3大電子設計自動化（Electronic Design Automation；EDA）業者角力戰場！繼新思（Synopsys）台灣研發中心擴編進度超前，益華（Cadence）在新任總經理張郁禮帶領下，規劃將台灣研發中心人員擴充1倍以上，全力搶攻台灣新思旗下客戶群並開發前端科技新興市場，誓言奪回市場寶座；據了解，明導（Mentor）同時也規劃第三季將設立台灣研發中心，並延攬台灣新思研發中心主管劉樂群領軍，3大EDA業者本土戰雲密佈！

: E! m( K7 ?! M: ]9 P) D' e　益華目前除了5大產品平台：Incisive、Encounter、Virtuoso、Allegro及DFM外，每年更以龐大研發資源投入先端半導體技術設計，台灣行銷總監馮元掄表示，目前益華與各大晶圓廠包括整合元件（IDM）及晶圓代工業者、設備業者及設計公司共同合作的X-Architecture逐漸被市場接受，並從90奈米演進至65奈米製程技術，應用層面也從PC繪圖晶片擴散至網通領域；同時，益華積極與台面板廠共同開發SoP（System on Panel），將傳統SoC設計手法套用在面板系統電路設計上。
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　不僅益華重新調整台灣市場策略轉趨積極，據了解，明導近期也展現台灣市場佈局大動作，不但延攬新思研發中心高階主管劉樂群，同時規劃在第三季宣佈設立台灣研發中心，也使得3大EDA業者在台灣研發中心已全數到齊。儘管新思全球營業額僅次於益華，不過，新思紮根台灣坐擁第一的位置，已成為益華、明導等業者亟力拿下的目標。

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作者: andy2000a    時間: 2006-10-25 03:44 PM
taiwan 跟本沒有 mentor
從以前 cic  和  cadence 掛一起

我們都只學 cadence or synopsys  ..

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作者: imems    時間: 2006-10-31 10:00 PM
Calibre 就是 mentor 的  業界 最常用 驗證軟體

原帖由 andy2000a 於 2006-10-25 03:44 PM 發表
taiwan 跟本沒有 mentor
7 [! N9 f: {% L4 z% s  ?6 J0 g$ A. A1 g從以前 cic  和  cadence 掛一起
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0 `1 h* }' N0 x  r6 y+ c我們都只學 cadence or synopsys  ..

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作者: yhchang    時間: 2008-2-13 03:41 AM
教育界的Tool
; P* ^6 O$ \: ^' p, Q3 ?" J1 }全部都被 Cadence  Synopsys  Mentor三家吃走了吧
5 c. D: t- z% S+ t% r: lCalibre 是這幾年才廣被採用的 DRC/LVS/LPE的軟体
1 u, O) G* G4 [! p3 J; |% m1 c1 c在這之前  Dracula已經在學術界使用了將近五到七年的時間

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作者: cashflow    時間: 2008-11-25 03:43 PM
應當說各有千秋，呵呵
* w6 ?  Z7 K+ t/ u& y8 R5 J6 g% z其實這幾家公司的人跳過來跳過去，都是在這幾家公司裡面的，呵呵

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作者: wellsjong    時間: 2009-10-16 03:03 PM
板主，這個問題包涵太大了，像是哪邊戰力強，如果是問Analog這塊的話，我會說是Cadence。如果是Digital那我就會投Synopsys.

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作者: heavy91    時間: 2010-7-19 02:14 PM
標題: 2010上半年Cadence重點新聞彙整

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6/30/2010	SiS Adopts Cadence Technologies for Advanced SOC Designs
6/21/2010	Cadence Completes Acquisition of Denali
6/14/2010	Cadence Delivers Extensive Support for TSMC AMS Reference Flow 1.0 for 28-nm Process
6/14/2010 / v, U' u2 N5 x8 @5 c4 D	Cadence Delivers TLM-Driven Design and Verification, 3D-IC Design and Integrated DFM Capabilities to TSMC Reference Flow 11.0
6/14/2010	Cadence Kick-Starts UVM Adoption with Open-Source Reference Flow Contribution to UVM World
6/11/2010	Cadence Announces Comprehensive SOI Design Hub
5/24/2010	Cadence and IBM Team to Develop Leading-Edge IP
5/24/2010	Rapid Bridge LiquidIP Now Available as Part of Cadence Open Integration Platform
5/20/2010	Computer Simulation Technology Announces Closer Cooperation with Cadence
5/14/2010	Cadence to Acquire Denali
5/7/2010	Cadence Accelerates SOC Realization, Reduces Costs with New Open Integration Platform
5/3/2010	VIA's Centaur Achieves Significant Benefits Using Cadence Virtuoso Space-Based Router at 65nm
4/26/2010	Cadence Debuts Verification Computing Platform
4/21/2010 / B2 ]' D+ c5 x0 m/ G2 J	Cadence Contributes Technology to Boost Verification of Complex Mixed-Signal Chips
4/14/2010	HiSilicon Adopts Cadence Mixed-Signal and Low-Power Technologies
4/14/2010	LSI Adopts Broad Range of Cadence Mixed-Signal Technologies
4/14/2010	TSMC Expands Cadence Tool Support In Integrated Sign-Off Flow By Adding Synthesis, Place and Route, and RC Extraction
3/29/2010	Cadence Teams with AcAe to Accelerate Transition to Allegro PCB Products
3/24/2010	Renesas Cuts Design Time by Half on Large-Scale Consumer SOC by Using Cadence Encounter Technology
2/2/2010	austriamicrosystems Expands Reliance on Cadence Technology to Achieve Seamless Mixed-Signal SOC Designs
2/2/2010	Cadence EDI System 9.1 Addresses Productivity Crisis for Complex SOC Design
2/1/2010	Cadence Software Validated on STARC QA Database
1/27/2010	Renesas Adopts Cadence Virtuoso Technology for Mixed-Signal and Analog Design
1/25/2010	Cadence OVM SystemVerilog Solution Enables More Thorough Verification at Mitsubishi Electric
1/25/2010	NEC Electronics Adopts Cadence Encounter Digital Implementation System for 40-nm ASIC Designs

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作者: heavy91    時間: 2010-7-19 04:17 PM
標題: 2010上半年Mentor Graphics重點新聞彙整

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Mentor Announces Commercial Linux Platform for Freescale Processors Based on Power Architecture Technology	6/23/2010
Mentor Graphics Questa Functional Verification Platform Adopted by Mindtree	6/21/2010
Mentor Graphics Extends TSMC Reference Flow 11 with Support for ESL and Integrated Design and Manufacturing Closure	6/17/2010
Mentor Graphics' Olympus-SoC Place-and-Route System Now Supported By X-FAB	6/17/2010
Mentor Graphics Provides Comprehensive Verification Support in TSMC AMS Reference Flow 1.0	6/17/2010
Mentor Graphics Working with TSMC to Speed SOC Verification with Calibre Automatic Waivers	6/11/2010
Mentor Graphics Announces Calibre xACT 3D for Fast and Accurate Extraction Using 3D Field Solver Technology	6/8/2010
Mentor Graphics Underscores Support for OVM and Extends Support to UVM Across Multiple Products	6/7/2010
Mentor Graphics Introduces Precision Rad-Tolerant Product for Advanced Radiation Effects Mitigation	6/3/2010
Mentor Graphics 0-In Formal Version 3.0 Brings New Level of Automation to Formal Verification	6/1/2010
Mentor Graphics Releases 0-In CDC Version 3.0 to Support Verification Needs of Larger, More-Complex Designs	6/1/2010
Mentor Graphics Announces New FPGA Synthesis Innovation in Precision Synthesis 2010a Release	5/20/2010
Mentor Graphics and NetLogic Microsystems Establish Strategic Multi-Core Collaboration for Embedded Linux	5/19/2010
Valor Releases Major New Functionality In the vSure DFM Product	5/19/2010
Mentor Graphics Veloce Delivers 400X Acceleration for OVM Driven Verification	5/7/2010
Mentor Graphics Calibre InRoute Delivers True Manufacturing Sign-Off During Physical Design Closure	5/3/2010
Mentor Graphics and Lauterbach Collaborate On Hardware-Accelerated, Software Development and Debug Platform for SOC Verification	4/27/2010
Mentor Graphics Selected as a Key Freescale Commercial Linux Strategic Partner for QorIQ and PowerQUICC Processors	4/26/2010
Mentor Graphics Announces Multicore Solutions for Symmetric and Asymmetric Multiprocessing	4/22/2010
STMicroelectronics Adopts Mentor Graphics Veloce Emulation Platform for Its New Generation of Set-Top-Box Chip Sets	4/15/2010
Mentor Graphics Extends DO-254 Platform Offering with Enhanced HDL Coding Standards	4/14/2010
Mentor Graphics ReqTracer Automates Requirements Tracking and Reporting for Electronic Design Projects	4/5/2010
Mentor Graphics and Platform Computing Optimize Use of Veloce Emulation Systems as Shared Resources	3/30/2010
SMIC Bases DFM Sign-Off Strategy on Mentor Graphics Calibre Platform	3/30/2010
Mentor Graphics Calibre LFD Certifications at TSMC Now Include 28-nm Process Node with TSMC UDFM Engine	3/23/2010
The MathWorks and Mentor Graphics Outline Joint DO-254 Workflow for Model-Based Design	3/23/2010
Mentor Graphics Acquires Valor Computerized Systems	3/18/2010
Mentor Graphics to Extend Cooperation with STMicroelectronics for Advanced Chip-Development Design Solutions	3/16/2010
Mentor Graphics Adds AMBA 4 Verification IP to the Questa Multi-View Verification Components Library	3/10/2010
Mentor Graphics Introduces FloTHERM IC for Semiconductor Package Thermal Characterization and Design	2/25/2010
Dongbu HiTek Adopts Mentor Graphics Eldo for Optimized Cell Characterization Flow	2/23/2010
Mentor Graphics Eases Android Development with Support of Inflexion Graphical User Interface on the Zoom OMAP36x-III Mobile Development Platform	2/15/2010
Mentor Graphics Enhances Signal and Power Integrity Solution with Full-Wave 3D Analysis	2/3/2010
Agnisys Announces Support for OVM Register Package in IDesignSpec	2/1/2010
Mentor Graphics Catapult C Adds SystemC Synthesis and Expands Full-Chip Capabilities	1/25/2010

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作者: heavy91    時間: 2010-7-19 04:30 PM
標題: 2010上半年Synopsys重點新聞彙整


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SVTC Technologies Selects Synopsys' Manufacturing Tools to Accelerate Time to Commercialization	7/14/2010
Open-Silicon Integrates 50 DesignWare Interface and Analog IP Products with 100% Silicon Success	7/7/2010
ARM, IBM, Samsung, GlobalFoundries and Synopsys Announce Delivery of 32-/ 28-nm HKMG Vertically Optimized Design Platform	6/17/2010
PrimeTime 2010 Scales Timing Analysis Beyond 500 Million Instances	6/17/2010
Synopsys Delivers Optimized Lynx Design System for Common Platform 32/28-nm Technology	6/17/2010 6 A  G: X7 S* b2 S' a6 I, Y1 _
Synopsys Unveils Galaxy Characterization Solution for Standard Cells, Complex Macros and Memories	6/17/2010
Synopsys Unveils StarRC Custom 3D Extraction Delivering 20X Speedup	6/17/2010
Synopsys Delivers Comprehensive Custom Design Solution for TSMC Analog/ Mixed-Signal Reference Flow 1.0 & N, ^; s" ~- T( F1 c5 |	6/11/2010 9 d: x: i$ x. L& @9 }
Synopsys to Acquire Virage Logic	6/11/2010
Synopsys and IEEE-ISTO Launch Technical Advisory Board to Evolve Interconnect Modeling Standard " s, N  X: S7 ?+ }4 q* y3 w! H	6/7/2010
Synopsys Announces Synphony HLS Support for Xilinx Virtex-6 FPGAs	6/4/2010
Synopsys Press Publishes "The Ten Commandments for Effective Standards" / e8 m* r. i, O0 q	6/4/2010 7 R; _; n. u  V% w
Synopsys Collaborates with SMIC to Deliver USB Logo-Certified DesignWare USB 2.0 nanoPHY in SMIC's 65-nm LL Process Technology	5/13/2010 - v# i4 e  d. Z7 d9 d, R3 d" |/ w8 Q
Latest Synopsys IC Compiler Release Delivers More than 2X Speed-Up, Enhanced In-Design Technology and Production Support for 28/32nm	5/7/2010
Synopsys Unveils Ethernet Controller IP with New Audio Video Bridging Feature . m" K8 |8 A3 Z% `: X	5/7/2010 8 Y; Y) ~& X! D4 x! E& B8 h
Synopsys Launches Industrys First MIPI DigRF v4 IP 5 N# P6 T% y7 v8 X) S0 F7 C	5/3/2010 2 M3 \# ?5 n" y7 V
New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces ' |! j4 U% o! ]! z, o2 N	4/28/2010 ( |# I" L4 b9 D5 w3 V* i
Synopsys Announces Support for Actel's New SmartFusion Intelligent Mixed-Signal FPGAs	4/22/2010
Synopsys Introduces the HAPS-60 Series of Rapid Prototyping Systems 9 H9 H1 D1 Z: Z1 b4 d	4/19/2010 2 \' g& X- T! k3 z
Synopsys Expands IP OEM Partner Program with Two New Members	4/14/2010 7 `6 h2 N. O* m& G; m- W
Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards In a Single PHY	4/7/2010 , d( X  m$ D- \. p9 n8 M$ w
Synopsys' DesignWare SuperSpeed USB 3.0 IP Receives USB-IF Certification # v0 I5 P' n& k( Z9 t' U	4/5/2010
SiliconBlue Selects Synopsys as FPGA Synthesis Partner for Its iCE65 mobileFPGA Family ; `- r! h' [1 Z+ S	4/1/2010
Synopsys Galaxy Implementation Platform Enables First-pass Silicon Success on Infineon's 40-nm X-GOLD 626 Wireless Product	3/30/2010 + [- |$ |" P* p% V8 J: K" w' h8 z
Design Compiler 2010 Doubles Productivity of Synthesis and Place-and-Route	3/29/2010 2 Z5 i  _% t$ J9 \( v
Nationz Technologies Achieves First-Pass Silicon Success with CustomSim Mixed-Signal and VCS Functional Verification Solutions ' E0 D& e+ `6 B: E; p; ~	3/23/2010 . |+ B( S  [7 p7 S1 w' ~/ g: S
Renesas Technology Adopts Synopsys Proteus OPC for 28-nm Development * w7 P" S7 c' Y% D: f9 ~	3/23/2010
Synopsys Completes Acquisition of CoWare % D) e; p  F* ?, b	3/23/2010 ' G! y, c( d  E1 J& O' w
IMEC and Synopsys Collaborate on 3D Stacked IC Development ; H$ e- G' j$ w4 o	3/10/2010
Synopsys Galaxy Custom Designer Accelerates Analog/ Mixed-Signal Engineering Productivity with Built-in DRC Visualization and Correction & _1 c' v5 p- i& N	3/10/2010   l# f# w( _  V2 @( }6 c5 C
Yamaha Tapes Out Graphics Chip with Synopsys Design Compiler Graphical	2/9/2010
APAC IC Adopts Synopsys Galaxy Custom Designer Solution for Analog/ Mixed-Signal IC Design Services	2/8/2010
Synopsys to Acquire CoWare - V5 P: _% ~6 w; [! `' j! P	2/8/2010 4 y2 J/ q8 ?* n. S% V. [" W
Synopsys Acquires VaST Systems Technology	2/3/2010
Synopsys Expands DesignWare IP Portfolio with MIPI IP Solutions	1/25/2010
Synopsys Launches DesignWare HDMI 1.4 Tx/Rx Controller and PHY IP Solutions for 40-nm Process Technologies	1/25/2010
Toshiba Information Systems Standardizes on VMM-LP Low-Power Verification Methodology	1/25/2010 / f, |0 U% F% e2 {9 E# a
Synopsys Announces DesignWare Protocol Analyzer for Verification of SuperSpeed USB 3.0-based Designs	1/13/2010
Synopsys Introduces SystemC TLM-2.0 SuperSpeed USB 3.0 Models * A% d7 P9 K- h+ E	1/12/2010
Synopsys Multicore Technology Speeds Timing Sign-Off by 2X	1/11/2010 : ?- q  Z0 f% F; x

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作者: ranica    時間: 2013-11-26 09:29 AM
Field Applications Engineer

  X! \# g& Z! V) l7 r+ d4 F公      司：One world top EDA company
工作地点：北京

Position Description:      
3 r0 ^0 u4 Z- d- The Field Applications Engineer is responsible for working directly with customers in key technical pre-sales and post-sales roles to provide architectural and design consulting on the best use of Intellectual Property software programmable cores in various different applications including Wireless Communications, Audio processing as well as Image pre and post processing in a customer''s ASIC design.
* B8 I9 y* C( ?, x. f$ S- DPU cores are used by the world leading semiconductor development and supplier companies. As the Field Applications Engineer, you will be working with customers on the next generation designs. In the Wireless Communications application, customers are using cores in their 2G, 3G, 4G (LTE and LTE-Advanced) modem systems for User Equipment and Infrastructure products. You will be working with industry leading customers on their next generation designs.
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! |1 H! R) Q* s8 e, }) m" x5 BResponsibilities:
5 [- O/ i2 Z$ k( N7 }- Provide technical presentations, seminars, and demonstrations of products, and working closely with the field sales organization to achieve revenue targets
1 E) A' H$ {; D$ [  R; w9 Y) Z% C-Fulfill a pre-sales role that includes providing technical insight about products to prospects, optimization of customer''s software code during an evaluation, and processor performance and implementation benchmarking
- {1 N+ I! \9 k( l% O1 @7 x3 u1 W-Manage technical accounts and champion customers’ technical issues within the company
-Primary responsibility for assigned areas and other duties as required

Position Requirements:
) f7 k4 o; j7 v+ ~-BS in EE/CS or equivalent and 6+ years’ industry and technology experience with 4+ years experience as a Field Applications Engineer or Applications Engineer
-Experience with DSP architectures, DSP filter programming
" d5 O2 @# a$ c( J- x4 {-Experience and understanding of 3G and 4G PHY (Layer 1) algorithms
-Experience and understanding of ASIC SoC design and implementation is a big plus
-Prior FAE/AE experience is desired. An MS in EE/CS is preferred. Some degree of travel may be involved, depending on location and need

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作者: innoing123    時間: 2014-2-6 08:54 AM
Cadence To Buy Forte
High-level synthesis market heats up as complexity and early tradeoffs become more difficult.

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作者: ranica    時間: 2014-7-16 08:21 AM
IC CAD 工程师

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工作地点：上海

职位描述
$ _  ^0 s& V$ A5 T* _( m- y( L6 M1、IC设计研发团队服务器的搭建与管理，保证服务器的稳定、高效以及数据安全；
2、负责EDA工具及相关license的安装和维护,优化相关环境变量及软件设置，确保设计环境的正常运作，提升自动化程度；
3、为IC设计提供EDA工具技术支持及项目支持，使用perl,shell以及tcl等编写自动化脚本，优化设计流程，提高设计工作效率；
/ a, g! N$ B: }8 t" W! c3 V4、协助完善IC设计流程。

岗位要求：
1、计算机、自动化及电子相关专业本科以上学历；
2、两年以上相关工作经验；
8 y5 D6 Z1 S; B/ \3、具备撰写Perl/ C-shell/TCL等编程脚本的技巧和能力；
8 v" K  \5 n% B" O4、熟悉UNIX/LINUX操作系统，熟悉多种EDA工具；
5、具有IC设计软件使用经验或了解IC设计流程相关知识者优先考虑；
6. 具有良好的沟通能力、分析问题能力、较强的协调能力，以及团队合作意识。

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作者: ranica    時間: 2014-8-19 05:17 PM
Senior Engineering Manager
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公      司：One world top EDA company

0 r- K' m4 @* \& {* V6 a- nPosition Description  
1. World’s leading design companies rely on xx technologies to deliver the latest design innovations in consumer,
mobile and enterprise electronics. We are looking for a strong software engineering leader to join our team and contribute to the continued growth and success of the company’s flagship products, including ADE and AMS Designer.
2. In this high-impact career opportunity you will be responsible for delivery of cutting-edge features in mixed-signal simulation and the Virtuoso environment, including technology leadership, team development and people management.
3. You will also work with a cross-functional team in Beijing and North America to ensure that our software is developed, tested, and documented with high quality.
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' ]7 Q4 Z& p# W- V: K( D' }! nPosition Requirements  
Requirements:
1. Experience managing software development teams in the EDA or related industry
2. Successful delivery of software products over multiple release cycles
3. Proficiency with build and version-control systems
4. Strong software engineering skills in C/C++ and familiarity with Linux/Unix development
  e$ u, A9 {3 [5. Excellent written and oral English communication skills
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& Q! F5 w& |  \! wPreferred skills:
1. Prior experience with analog, digital or mixed-signal simulation using SPICE, Spectre and Verilog languages
2. Exposure to the Virtuoso environment or other electronic design platforms

Education:
& ]0 l* c. L/ H1 YB.S. or higher in engineering, computer science or related field.

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作者: tk02561    時間: 2014-10-21 08:37 AM
創意電子採用Encounter數位設計實現系統在台積16奈米FinFET Plus製程完成首件量產設計定案
) {6 f9 h+ b% N# pCadence數位解決方案協助創意電子提升2倍系統效能並完成1.8億邏輯閘SoC設計

台灣新竹(2014年10月21日) -全球電子設計創新領導廠商益華電腦(Cadence Design Systems, Inc.) (NASDAQ: CDNS)與彈性客製化IC領導廠商(Flexible ASIC LeaderTM)創意電子(GLOBAL UNICHIP CORP.，GUC)宣布，創意電子在台積電16nm FinFET Plus (16FF+)製程上，採用Cadence® Encounter®數位設計實現系統完成首件高速運算ASIC的設計定案(tape-out)。創意電子結合16FF+製程的效能優勢並採用Cadence數位解決方案，可讓這個ASIC的操作時序提升18%、且功耗減少28%，在其應用的系統上更可以達到兩倍的效能。
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創意電子運用Encounter數位設計實現系統解決16FF+的設計實現挑戰，包括雙重曝光和FinFET設計規則檢查(DRC)、時序和電流變異性，以及處理量要求。Encounter系統還能提供以下優點：

9 H. P7 G/ F  a# Q6 k7 E•        正確建構、完善的雙重曝光和涵蓋平面規劃、配置、以及繞線至電子和物理簽核的FinFET流程
. g( w" ?9 @1 y, l•        與Cadence的Litho Physical Analyzer和CMP Predictor完美整合，達成可製造性設計(design for Manufacturing, DFM)
•        採用大量平行的多執行緒(Multi-threaded)GigaOpt和NanoRoute技術，有效掌控DRC規則和設計尺寸
) E! X! N8 [) m- H1 q0 z' a•        改善SoC效能和功耗的GigaOpt先進晶片內變異(advanced on chip variation, AOCV)和佈線導向設計

• 創意電子總經理賴俊豪表示：「創意電子身為ASIC設計的先鋒，我們必須要能及時將非常複雜的設計提交給客戶，Cadence的工具和團隊在這方面提供了充分的協助。Cadence在台積電先進製程的豐富經驗讓我們選擇與Cadence共同研發旗下設計。在完成這首次16FF+產品設計定案前，我們也已經運用Cadence方案完成數個16nm測試晶片並且獲得非常好的量測結果。藉由Cadence與創意電子團隊的通力合作，我們才能達成在3個月完成1.8億邏輯閘生產設計定案的目標。」

: Q& j, \- n* T' B   Cadence數位暨簽核部門資深副總Anirudh Devgan表示：「Encounter數位設計實現系統的設計能為100M+高效能和低功耗設計提供最有效率的方法。Encounter系統已獲台積電運用於16FF+製程的認證，讓創意電子和Cadence其他客戶在先進製程上快速達成設計定案更有信心。」

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