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09:00~09:30 / Registration9 X% K: u; |% N7 C$ @9 b
5 ~& X8 D9 u! T5 Q09:30~09:40 / Automatic floorplan for design exploration to get the best result j3 A% l6 z" Z& B* S+ ^, ~' ?/ W9 U; g; ~" s4 H
09:40~09:50 / Balanced clock tree to reduce process variation effects - |& h/ j, h) {% x7 G& F0 ?
7 Z# U8 x& \1 Y: v& i, z& I09:50~10:00 / 32nm support for the very advanced technology . \% N0 Q$ _) n2 p
6 `1 o* @& T* Z10:00~10:10 / Post route optimization and SI closure productivity ) T! O+ X9 V4 X8 S' o8 W. M5 [$ D0 j2 Q4 M! `( \. B
10:10~10:20 / 100% MMMC support in the entire implementation flow# Y5 N$ R* U1 j! e
2 q: t5 S1 x) Y# \! r7 d* \, q7 Y/ p10:20~10:30 / Dynamic power optimization and low power CTS for power reduction 3 M6 U3 Y u) f3 v- P# F& x7 q. m: Q6 p7 Y- n
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10:30~10:50 / Break . M( Q8 v, |( o6 Y7 L9 O: z 8 |: ~' B# f# l; a) S& B 8 l: ^3 {4 z; s0 f3 { - U% ]1 P5 Q3 j( _ O: k10:50~11:00 / Encounter Power System for new generation power integrity analysis 5 ~: ~, c) Y0 N3 ?/ ]" [0 d2 M m
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11:00~11:10 / 3 very advanced statistic applications for better performance : @. P9 Y( L1 ? P( c& \2 H: E! q7 G/ o1 R7 |$ H8 e3 w# r
11:10~11:20 / Active Logic Reduction Technology (ART) to handle big chips z) V, o& y$ l3 c- u
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6 Y3 M: F/ z2 x+ O% w k3 a _$ Y9 \2 ^- i+ U9 n( e g, s: y$ R11:20~11:30 / Constant run time and memory usage improvements 5 ^4 @$ G8 r& U$ n$ ]5 H# ~" S( s& \6 n& t+ Z0 I& o8 b
11:30~11:40 / End-to-end parallel computing support% `1 l8 ]; u; P5 L5 d9 d+ n
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11:40~11:50 / Encounter Foundation Flow for ease of use and productivity gain' \9 ]- A- n) t. E2 A' o M