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標題: My chip was burned down, need your help! [打印本頁]

作者: wjsh 時間: 2008-10-26 05:35 PM
標題: My chip was burned down, need your help!
Hi all,
My chip was burned down, it was burned after a long operation during tests. It's a 1A li-ion charger IC. I have tested several tens chips, and 2 of them were burned. I saw Supply current is current limited by my setting(2A), VBAT current is ~30mA(E-load), and then chip was burned down.
1) Could someone help me to figure out what the possible causes might be in your experience?
2) Will latch-up result in this condition? When the circuit might cause latch-up condition, will all chips fabricated latched-up? When latch-up condition happens in some chip, will this chip be damaged and never be powered up or never works?
3) I saw VBAT consumed only ~30mA(it's measured by E-load, maybe transcient current is very large), but VIN consumed very large current(current-limited by supply), does this condition imply something?
Thanks for your help.

作者: finster 時間: 2008-10-27 01:31 AM
我建議你把你的電路圖貼上來,若是有公司機密問題,也可以function block來表示,或者把電路size拿掉,或者把其中幾個關鍵的電路用block表示
不然,以文字來描述,很難猜出你是用何種架構,其中幾個關鍵的電壓節點的情況又是為何

一般作power IC會燒毁,如果不是function上出現short的問題,就是你的metal畫的太細,導致在流過大電壓時因為metal density的問題而把IC燒掉,故而,這兩點需先弄清楚
再來,要發生latch up需有其特殊條件,並不是所有電路都會發生latch up,建議你把IC去照亮點,然後看看發處為何,然後再分析發亮處的layout處的畫法為何,元件擺法為何,這個樣子比較能夠確定是否為latch up
因為你沒有貼上電路圖,所以對於Vbat和Vin的關係為何無從推知,當然,也無法幫你想問題為何

作者: wjsh 時間: 2008-10-27 11:02 AM
Thank you very much, finster.
But if that's function problem, all chips might be burned, am I right?
Only 2 of several tens chips were damaged, until now.
For the charger IC, its structure is very much like LDO.
Most of times, I was trying to re-construct the burned-down condition, but in vain.
It's hard to see the burned condition, almost every chip work normally except those 2 chips.
Trying to figure it out.
Thank you, again!

作者: semico_ljj 時間: 2008-10-27 05:11 PM
还有可能是大电流下，引起了LatchUP！可能版图出现的问题居大！。。

作者: finster 時間: 2008-10-28 01:01 PM
想請問你一下,你說你的電路近似是一個LDO,那提供那個output voltage and current的device是用PMOS還是NMOS,其size為多大,這顆MOS是在chip內部還是外部,若在chip內部,那它的Drain和Source接到VDD以及到output的metal width各為多少?
另外,請問一下,你的外部電路有用到電感或者BJT嗎??因為你只說你的電路近似LDO卻沒有細部說明,我實在不知道你真正的架構是那一種,因為不同架構有不同可能發生燒毁的可能

最後,在Power IC中,在function上最容易發生燒毁的地方絕大部份都在Power MOS,因為那個地方會流過大電流,如果你本身的metal width不夠粗且寛的話,在電源電壓一開始起來時,若沒有over-current protection電路機制,很容易會因為流過大電流而燒毁,同時,如果size不夠大也會造成同樣燒毁的可能,另外,還有一種就是你外面有接電感之類的被動元件也有機會發生

作者: wjsh 時間: 2008-10-28 02:59 PM
Thank you finster.
I used PMOS, it's size is about (50000/0.8) due to Ron is not concerned so much.
I used Top metal width=18u*6 strips due to rule. There is no external inductor or BJT, little inductance might exist because I used socket and wrapped cu-line to test.
Thank you for your help.

作者: alab307 時間: 2008-10-28 10:52 PM
看起來像是Latch-up
實驗方法
1. 降低Supply限流值, 避免IC燒掉
2. 想辦法將IC加溫 (用焊槍or吹風機)
看有沒辦法出現大電流
3. 出現大電流後, 看Supply電壓值
if 1.x Volt, 那有可能是Latch-up

作者: finster 時間: 2008-10-29 02:15 AM
從你的回答中我大概知道了你的電路
那再問一下
你的chip中有沒有一個叫作start-up電路,或者稱之為soft-start電路,這個電路的功用乃在當電源電壓一開始起來時,它會讓你的Power PMOS的Gate電壓不會維持在0V,而是類似保持在某一個電位,或者和電源電壓大概差一個電位
另外一個則是你的chip中有沒有一個叫作over-current protection電路,或者叫作over-current limit電路,它的功用是當你的Power PMOS流過它所能夠容許的電流上限時,會把Gate電壓限制住,或者將Gate電壓拉到Vin電壓
如果你的chip內部沒有這兩個電路,那燒毁的原因就大概知道了,若有,那需再往其他因素思考

作者: wjsh 時間: 2008-10-29 01:21 PM
Hi finster, alab307, semico_ljj,
Thank you for all your inputs.
I have tried the latch-up tests as alab307 suggested, it seems chip works normally.
Besides, I have a soft-start circuit for ~2ms to clamp Gate voltage from VIN to desired voltage, so I think it's OK for power-up sequence because the burned situation seems not happened during power up.
Thank you all, once more.

作者: finster 時間: 2008-10-29 11:41 PM
從你的回答來看,你們並沒有over-current protection電路或者over-current limiting電路,再者,因為Power PMOS的size很大,故而,從你回答的size來看,應該可以流過1A~2A以上到輸出負載應該不是問題(我這是指在不正常的情況下)
不過,因為你們沒有限流保護機制電路,故而,只要有一些short或者負載電流突然間異常增加時,這顆IC有很大的機率會被燒毁,而這也是我在前面詢問你們的chip內部有無soft-start或者start-up電路以及over-current protection電路的原因

再來,我想再請問一個問題,因為你說你們有
soft-start circuit for ~2ms to clamp Gate voltage from VIN to desired voltage.
那重點來了,在soft-start期間,Gate電壓為何??在脫離soft-start時,VIN的電壓為何?此時Vout電壓為何?預期的Gate電壓又為何?
因為若這個function設計不對,那在脫離soft-start時,有很大的機率會有瞬間流過超出1A以上的peak current到輸出

作者: wjsh 時間: 2008-10-30 09:20 AM
Hi finster,
The soft start circuit is initiated by POR(level is about 3/4 VIN), after POR initiated the soft start is activated for ~2ms to ramp down Gate voltage from VIN to a desired voltage(for corner, it's maximum current vs this gate voltage is ~500mA). After that, loop will self control.
My question is, if the situation is marginally happened, it means the design is on the corner edge, then should be some chips will be damaged. But it seems only 2 is burned, that's my headache.
Thank you all.

作者: finster 時間: 2008-11-1 12:33 AM
希望你下次在詢問問題時能夠把簡圖貼上來,不然,有時真的很難回答
接續上次我詢問的問題
在圖A中的電壓為幾伏,是Vin呢?還是那一個電壓?因為此時在脫離POR時,你的PMOS的Gate電壓極有可能會因為Vout需要大的負載電流而導致OP在開始動作時會強拉到0V來對Vout作charge current,如此一來,在脫離POR的瞬間,PMOS極有可能會流過極大的電流而導致IC燒毁
而你的IC只有幾顆會被燒毁,這個原因可能出自於POR的準位,因為POR的pulse無法設計的很精準,就我個人所知,POR電路會依據你的R-C值和Power supply ramp速度而來決定pulse的長度,而且這個POR level又和製程又有很大的落差差距,你的POR level愈接近Vin才轉態會愈容易讓PMOS流過極大的電流,而愈大的電流流過metal愈容易產生熱,一旦metal層的溫度上昇又會帶動電流加速流動,而一旦電流的移動速度變快又再使metal層的溫度上昇而形成正向回授,最後便會導致IC燒毁一途
這種現象最常發生在電源電壓一開始起來,或者脫離POR切換到正常運作的function,或者負載電流突然間變大的情況都有可能發生IC燒毁的問題,而要避免這種問題,通常都會加一個over-current protection或者over-current limiting電路來抑制Power MOS流過大電流的情況

作者: finster 時間: 2008-11-5 12:53 AM
抱歉這麼晚才回覆,因為這幾天在作project的debugger
你提到的TEMP是指那一點的電壓,再跟你確認一下各個pin腳的關係
VIN是外部的電源電壓
VBAT是LDO電路的輸出電壓
那TEMP是那一個電壓,是參考電壓嗎??還是控制腳,它所看到的是Gate還是Drain或是Source

你們是在作pin-to-pin short時才會把IC燒毁,而且是VBAT和TEMP short在一起時才發生燒毁的情況,那此時,VBAT和TEMP電壓各為幾伏??VIN應該該是5吧
那你們chip內部有沒有thermo-protection circuit(熱保護電路),它是一種當chip內部的溫度高於某一個設定值時,會把Power MOS給shut-down的保護電路

從你們de-cap燒毁的地方來看,應該是瞬間流過Power MOS所能夠容許的電流,所以才會在Source部份有damaged,現在要確定的是TEMP這顆Pin腳的形態,還有燒毁的情況是因為瞬間流過所能容忍的電流造成的燒毁還是因為大電流造成高溫引起的燒毁

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