標題: 佈局年資7∼9年的你，請問你薪水多少 [打印本頁] 作者: jianping 時間: 2008-6-6 12:45 PM 標題: 佈局年資7∼9年的你，請問你薪水多少 僅共大家參考，投票不記名，請大家放心，結果供大家以後跟老闆談薪水用 ^_^ 9 v7 M Z$ d: U, h/ \" I+ N5 B+ f7 W+ k, {. W* ]9 D
[ 本帖最後由 jianping 於 2008-6-7 09:40 AM 編輯 ]作者: liu.leon 時間: 2012-4-17 05:41 PM 回復 1#jianping作者: ranica 時間: 2012-5-11 11:05 AM
招聘公司：A famous IC company 6 S8 R2 E! P% F# Q; U招聘岗位：Sr.IC Layout Designer ' n/ o' Y r% \. r9 h工作地点：Shanghai 3 f P/ y3 \ K1 }6 d/ t! _8 ]/ V3 z! z3 _% V( K
岗位描述：: h& ^/ y5 j+ i
Purpose: The primary objective of this role is to transform IC schematics and related design material into physical IC layout representations. Responsibilities: 1. Perform challenging IC mask design of advanced analog mixed signal and flash memory IC'S 2. Develop layout floor plans to optimize die size and circuit performance; 3. Plan and construct circuits, including critical signal and power bussing to analog layout guidelines; 4. Perform DRC and LVS verification of layout; 5. Other duties and when required. ; G9 ~# {2 t0 R7 p/ \7 q " x# G5 q& o+ y. f职位要求：" q! M) f6 Z& e4 k( y
Requirements: 1. Thorough understanding of IC layout design including use of CAD tools such as DRC, LVS and skill programs 2. Must be good at problem solving 3. Must have the ability to communicate effectively 4. Minimum of 4 years experience in IC layout. Use of cadence Virtuoso XL, Calibre Drc. Other Attributes Minimum of 4 years experience in IC layout. Use of Cadence Virtuoso-XL, P-cells, Calibre DRC/LVS Qualification Bachelor Degree or higher preferred作者: innoing123 時間: 2014-6-24 11:56 AM
Sr. Layout Engineer /Staff Layout Engineer ' B7 A! x( a- i! Y7 L8 i/ L1 E: m) I- w
公 司：one famous IC company 9 f' |, I, C2 t' P工作地点：上海 5 i5 m' s) J' ? $ X5 \; H7 M w$ J6 `. gJob Requirements: # r [% @$ o0 ~9 ~; W
-Work with circuit designers to build physical design floor-plan; # N8 Z6 T. d4 w' t0 U) q/ l-Complete the physical layout design with the constraints of circuit design requirements; : r2 V6 q- f S6 f$ g3 h-Verify the physical layout design to meet both circuit design requirements and process requirements; \+ H# d; m/ `$ x1 R-Use the advanced technologies to improve layout design quality and efficiency. * J4 I+ {$ _& `9 H, ^1 }( G( `) D% [3 f$ ^! G2 C+ E0 @
Qualifications: ( Q& U# q3 g% k; r$ u" o-College degree (or above) in Electrical Engineering or other related engineering field; : u* L0 W; O3 B3 \4 n0 a
-At least 4 years experience in layout design field with rich tapeout experience; 9 x) z5 k$ O" @" V6 P. @
-Good understanding of basic electronic principles dealing with circuit and layout design; 3 a/ }; h' p5 U& D( B' y6 O. h-Familiar with IC layout methodologies, flows and CAD tools such as Cadence virtuoso layout, Caliber physical verification; 3 b9 x U( b) x-Prefer experienced in PLL and IO design - @# G2 y; I; O% ]3 [( A-Patient, A good team player, Good communication skills; 6 n* A- ?% \$ O( T2 g-Can communicate with both written and spoken English.