Xilinx Virtex5 FPGA 結構與特性 - Chip123 科技應用創新平台

*Objectives
1 B3 i8 M( J* @) P8 f, ~After completing this course, the student will be able to:
, D) a' y! i( ODescribe both the feature enhancements of the V5 over the V4,
' ^8 X" m2 d/ F* t- f9 xand
& c. [1 ?" M$ rNew architectural features of the V5
! X2 P# L) G  L! HHave a fundamental understanding of how these features can be
+ r8 |8 Q. y8 gleveraged to bring about timing closure.
7 i( E6 `! i9 c3 B' V*Agenda0 A! h8 Z5 S* n" A# o
Overview (15 minutes)
5 T3 b: l5 ^7 SBrief Description of Differences between V4 and V5 (30 minutes
& I! Q3 {; h- s. KV5's new PLL and Use with DCMs (45 minutes)% C0 Z2 H! s6 G
Lab 1 – Introduction to the PLL/Architecture Wizard (30  h$ w5 U( \/ }) @; J
minutes)
" ]: q: c! k+ T  m* d$ vImproved Features in V5 (30 minutes)
( D6 z" h; s) ?# d) H; L; vLab 2 – Leveraging Improved Features (45 minutes)