Xilinx Virtex5 FPGA 結構與特性 - Chip123 科技應用創新平台

*Objectives
4 X' z5 E2 v2 C' g' ] x9 aAfter completing this course, the student will be able to:5 k L: v0 `4 @0 }- t8 F9 [/ ^
Describe both the feature enhancements of the V5 over the V4,5 i: E" m0 J9 P
and6 g$ g' g- m" G8 U# e) V0 @: U9 n
New architectural features of the V5
* B9 a6 i1 Q" X- UHave a fundamental understanding of how these features can be9 U- n- g$ C9 P3 g
leveraged to bring about timing closure.- B( x: v8 [! z. I' }2 s; Q
*Agenda6 ^$ z+ l8 H' @: o$ _* n/ C+ e
Overview (15 minutes)' f+ S P C& ?+ v) j
Brief Description of Differences between V4 and V5 (30 minutes
: f2 o5 S5 ~4 kV5's new PLL and Use with DCMs (45 minutes)
, w0 s% I+ T2 g1 k2 eLab 1 – Introduction to the PLL/Architecture Wizard (30
. l1 J5 F. V8 V& ]minutes)
$ l; f0 z( `. c6 L/ F6 XImproved Features in V5 (30 minutes)
) x" U. R8 u; E& v; C# ZLab 2 – Leveraging Improved Features (45 minutes)