Chip123 科技應用創新平台
標題:
徵求6X64記憶體VHDL
[打印本頁]
作者:
w10789173
時間:
2008-3-8 12:01 AM
標題:
徵求6X64記憶體VHDL
徵求記憶體6-bit data in 64個字組,不過不要用陣列的方式,很感謝大家提共意見,不過都不是實際記憶體電路的VHDL,我想要的是一個column decoder,一個row decorder,使用port map latch 64個,輸出要使用三態閘,個人想法如下:
! c4 i# v' a5 U5 E
LIBRARY ieee;
: h7 Q+ X: {# t1 k1 A- Z- e, k
USE ieee.std_logic_1164.all;
6 ^" l9 S4 q) y) r' n
USE ieee.std_logic_arith.all;
7 q6 G' x# J3 e
" F, p3 V* B5 B. I# }0 J8 ~
ENTITY memory_64 IS
* ? Q3 \6 G! p8 B* {
PORT(
! i* F' F5 m P4 p/ Z4 a
mem_in : IN std_logic_vector ( 5 DOWNTO 0 );
: J) E# r- N& G; O* f
mem_out : OUT std_logic_vector ( 5 DOWNTO 0 );
* F. i$ v. _: B; n9 r6 E
clr_l : IN std_logic;
5 @! M5 F6 [% x8 G' J7 |
mem_addr : IN std_logic_vector ( 5 DOWNTO 0 )
# i( R" c0 L6 N+ P; l! n( k
);
9 G2 m" t7 E% E, G/ p# P
1 o6 Q0 Y) ]3 _; k
-- Declarations
' R& `7 k) N3 H9 y
5 s- K+ l) A' x/ }+ B8 I" o4 `
END memory_64 ;
( C; Z% L2 K% x+ M9 |" J$ O* d
. i, y$ O- _* R, c5 i4 R0 }; B
--
+ j* d" D( Z9 b' h
ARCHITECTURE arch OF memory_64 IS
i- @$ D1 f0 j
-- column decoder
* F: i% U( H8 j- ?" R1 O q
component mem_coldec
" M" ]0 D5 g& R) G* `+ m! v8 t
PORT(
0 j/ N% D0 \9 o7 P
col_addr : IN std_logic_vector ( 2 DOWNTO 0 );
- |, P6 n* `. y/ k
col_sel : OUT std_logic_vector ( 7 DOWNTO 0 )
" Z4 o: L& @1 `( ^3 y8 K, Q
);
. ~# M# i q }$ R
end component;
" x4 _; W& T6 i
-- row decoder
( ^) j9 b7 E5 _7 J
component mem_rowdec
$ E# G3 E' b7 x
PORT(
5 \' _8 Z9 f" p, A8 i4 B) v- l+ r! w: u
row_addr : IN std_logic_vector ( 2 DOWNTO 0 );
% p0 e% U& f2 y: g+ @
row_sel : OUT std_logic_vector ( 7 DOWNTO 0 )
5 Z. u' u$ K1 M' s
);
6 r7 |; y, ? `$ z0 \. C
end component;
: b$ y# g& \2 K2 N- w: a d' ?
-- latch array
0 j2 y! i3 [* F9 L( u9 D
component latch_cell
3 g$ f, B) C* h ?
PORT(
$ \* H: m0 E' t3 g# Q) J
clr_l : IN std_logic;
2 _- X' U: a) b* U/ d/ `7 P* k$ u
col_sel : IN std_logic;
1 f: G: c' o, b* d
row_sel : IN std_logic;
% r5 K( _( V1 [$ U9 R+ L( Q" b9 x) W
data_in : IN std_logic_vector ( 5 DOWNTO 0 );
; h0 U w, N z9 b" n+ G
data_out : OUT std_logic_vector ( 5 DOWNTO 0 )
! Z) K4 U5 u* ^3 t6 {
);
8 m( y8 P) ^* e; Q& n6 S
end component;
, o2 ]5 \7 H& j# x @1 b
/ [' j" `" ^9 r8 B' Q( U) y/ {) ]* w
signal smem_out : std_logic_vector ( 5 downto 0 );
2 P. c. [7 w) |) M
signal scol_sel,srow_sel : std_logic_vector( 7 downto 0 );
3 j& @. I" k1 N+ P# }' N# x
BEGIN
/ m# u3 ^# l+ K, f) D2 ^
u_0 : mem_coldec port map(mem_addr( 5 downto 3 ),scol_sel);
9 H! q5 l: F2 W
u_1 : mem_rowdec port map(mem_addr( 2 downto 0 ),srow_sel);
/ d/ w+ c4 P0 |3 O
g0 : for i in 7 downto 0 generate -- column generate
+ Q/ V$ u( L# w3 | A; b
g1 : for j in 7 downto 0 generate -- row generate
g, E: L* K! b& t7 o1 h
u_2 : latch_cell
- V3 T5 i/ L3 I8 t A$ K: [
port map(
( m* P% S# R9 P1 S' f
col_sel => col_sel(j),
; @+ K8 f2 z: ~8 |6 X& v5 j
row_sel => srow_sel(i),
n4 p* f/ o5 D8 |
data_in => mem_in,
# @; q; S+ t# K* w; R7 ?- `
data_out => mem_out(i)
I2 b" }: D* s- K7 g' z
);
6 L: g! D+ Q% W5 I
end generate;
6 Q- G9 u/ k/ h
end generate;
7 N2 m8 h3 V( R: B% D4 _
END ARCHITECTURE arch;
6 W5 y6 b+ y. @- c
不過模擬很久,始終沒辦法寫進我想要寫的位址,試寫了很久,但是始終寫不出來,所以請大家幫個忙,不然那些範例網路上都有,有點急,請大家廣發建議,感謝大家!
作者:
aiken
時間:
2008-3-9 03:15 AM
標題:
Try to read how other people working on ram using VHDL
http://tiny-tera.stanford.edu/ti ... ibm-ssram-dist-1.1/
7 Q9 N7 Z1 F& e2 r
9 J; E# x6 {' v8 M3 V! I: @0 c
You are designing ASIC ram? or use it in FPGA?
作者:
w10789173
時間:
2008-3-9 08:05 AM
Thanks for your solutions!
6 A8 K( m0 j( [5 `3 D7 D
: x, m+ D4 }0 f3 w! k: L, B0 k4 n
That is what i want it!
! }% S) H! B2 n) _. ~( |% W: p
* o) E0 F4 J: D" T5 V
This question already slved, please do not reply anymore.
4 g# Z% h7 [9 _# E+ g5 Y+ F* @6 _
' ~& K% f5 l- S
Thanks again...
歡迎光臨 Chip123 科技應用創新平台 (http://chip123.com/)
Powered by Discuz! X3.2