標題: FPGA verification Engineer most difficult job functions? [打印本頁] 作者: mister_liu 時間: 2011-7-18 05:19 PM 標題: FPGA verification Engineer most difficult job functions? 招聘公司：A famous IC company# O! u% D6 \4 I
招聘岗位：Senior FPGA verification Engineer7 A! O. Y% h8 X( s$ V/ m; f c* u
工作地点：Shanghai ; }$ i! R. x5 L 4 J% q8 _4 O- u3 Y2 B; o* @. u岗位描述：8 {9 A" ]3 Y( C2 ~& Y9 N# C) J3 B$ f4 f
Job Responsibilities 1. Port whole chip to Altera Stratix4 FPGA development board 2. Anticipate the HW/SW co-simulation environment building 3. Help debug the IP such as DMA, Memory controller, Display Unit5 L6 [8 \6 }! i' y
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Job Qualification 1. CS or EE Master is preferred, 3~5 years of relevant experiences 2. Altera FPGA verification experiences 3. Familiar with Altera Sigal TAPII 4. Familiar with Oscilloscope, Logic analyzer 5. Familiar with ARM SOC 6. Familiar with Verilog or VHDL6 \ ?- _) J8 A8 J
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能者與意者請email研發簡歷與chip123聯絡。作者: ranica 時間: 2011-7-19 05:40 PM 標題: Senior Design & verification Engineer 招聘公司：A famous IC company& N. D ~% |0 s% d& J
工作地点：Shanghai , D# K+ f8 ?* T) k+ e& h! \2 N0 n1 y
岗位描述：) D) ~& }0 f+ r# T% s1 j
Job Responsibilities 1. Design AXI NOR flash controller, AXI SDRAM controller 2. DDR2/DDR3 IP integration and verification 3. FPGA DDR2/DDR3 PHY integration 4. Write test plan on memory controller 5. Write C test cases to memory controller 6. Be responsible for all the techniques of memory controller6 E+ O0 x2 ]: l8 S+ O/ l
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职位要求： : U( k5 A. S" {! Q0 Z0 lJob Qualification 1. CS or EE MS/BS , 3~5 years of relevant experiences 2. Verilog or VHDL, C language 3. Familiar with memory controller including SDRAM, DDR2/DDR3 4. Be familiar with AXI, AHB, APB protocol 5. Assertion , Random test and coverage knowledge # u. \' w0 T6 ?- X( N3 U 7 {* K) i ` {& }' Y7 i! g能者與意者請email研發簡歷與chip123聯絡。作者: ranica 時間: 2011-7-19 05:42 PM 標題: (Senior) Digital IC Design Engineer （FE Design） 招聘公司：A famous IC company; j5 ^* F( ?8 q; z4 U
工作地点：Shanghai( P- o( Z; O, X
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岗位描述： , c$ o. w# X2 t7 lDuties • IP design and support for digital baseband of cellular phones • Digital SOC design and integration for chips6 R+ d' R2 ^* m t S I* J$ t
* I' b; U( j$ R( L6 `- V2 t* e: O职位要求： 5 B6 k6 l$ w* |0 I4 }. yRequirements • B.Sc. degree or above in Semiconductor, Electronics Engineering areas • 2 years or above design experience in industry • Good knowledge of design flow including documentation, VHDL/verilog coding, code check, equivalence check, synthesis, timing analysis and RTL simulation. • Good knowledge of AMBA AHB/AXI protocol is preferred. • Good knowledge in UPF/IP-XACT based design flow is a big plus. • Hands on experience in digital IC design EDA tools, such as NCSim/Questasim, Design Compiler, Formality, Primetime etc. • Good communication skill, will have frequent communication with foreign teams. • Good written and spoken English is mandatory. % }! ?( a4 z2 b& [, C $ v1 A$ y/ L# R( g能者與意者請email研發簡歷與chip123聯絡。作者: tk02561 時間: 2011-7-20 01:49 PM
招聘公司：A famous IC company 4 V) b7 j3 K: g/ _5 ~招聘岗位：Architectural Design Verification Engineer " M% d- r& Y) B% c工作地点：Shanghai4 P q {& C6 L1 C8 \0 V1 R6 x
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Responsibilities: To develop assembly programs for testing the compatibility of CPUs with the XX architecture. To develop and extend Perl programs which automate the creation of these assembly programs. To work with CPU architects to develop and implement test plans for the verification of new and existing XX architectural features. To work with simulator and core developers to run these verification programs, debug failures and identify necessary fixes to the models, cores, simulators and architecture: Z2 [# N6 [* z/ N
6 X7 N" G; J* M0 a5 e9 Z# n职位要求： $ ~( W" q ^! j& ]1 }$ s3 @% I" DKnowledge/Skills: Excellent programming skills and proven programming experience (post-graduate level research in a programming intensive field, or 3 years of industry experience) Excellent problem solving skills Ability to work independently, contribute to team goals, and to work with other team members in remote locations The following skills will be used on the job. Candidates with outstanding, proven programming experience in other engineering or scientific research fields would be given the opportunity to learn some or all of these skills on the job: - Knowledge of XX architecture - XX assembly language programming - Perl programming - Development experience in the linux environment Requirements: Education : BS in EE or CS (MS or higher preferred). Experience : Four years experience or more in related area. Systems : Unix, Linux, Windows. Language : Good English verbal skills plus reading/writing for documentation. Spirit : Good team spirit, professional, motivated and eager to learn combined with natural curiosity "to discover", "to know" and an attitude "to fix a problem". ; i$ O" A" L5 Y% F
8 W3 |% _ E5 ~5 z Q8 v! t能者與意者請email研發簡歷與chip123聯絡。作者: tk02561 時間: 2011-7-20 01:52 PM
招聘公司：A famous IC company f/ H M; F% r3 j* {; K+ J8 A/ a招聘岗位：CPU Core Design Verification Engineer Y# J9 t8 C7 t5 {工作地点：Shanghai3 I! }7 |( o2 t! f% @
9 @& |8 P+ l# i5 q+ y% G. lResponsibility: 3 S* G3 P2 N9 {* t' V; ^2 h X
Development and verification of XX microprocessor cores and products. ) d- r" W, X2 D! n6 H4 T" @ F+ J5 D4 { $ P' n/ E r _6 @" M/ z. k$ ]Knowledge/Skills:" Z+ v" A, Z* W* f+ x8 I+ |2 m
Strong microprocessor architecture and micro-architecture knowledge. / L$ G7 ]- W, V4 ~" nUnderstanding of XX architecture is preferred. , w4 S P7 t/ RGood logic and RTL design skills. ( c, }/ _8 m, G5 ?Experienced with CPU design verification, debug, and testing methodologies. 1 c. l+ U' H' E0 I2 T# P% O: V4 M
Good knowledge of common test methods and techniques (ie: regression, functional, random, structural, emulation ...) ) P2 m# w/ R5 RExperienced with building test environments, test benches, checkers, test vectors, assertions, coverage analysis, ... % S( O- L' u# M" r: _( |- e4 jGood programming and scripting skills, such as Verilog, System Verilog, assembler, Perl, Shell scripts, C, TCL, Windows Office, ...etc 2 N' Y. V" b- V% p2 | u0 N+ A6 o4 ~
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Requirements: ) f( v2 ^1 |+ Z) WEducation : BS in EE or CS (MS or higher preferred). 8 m4 D: ~% E4 U7 ^7 C# z5 kExperience : Four years experience or more in related area. $ M% K0 _- M6 }3 z( xSystems : Unix, Linux, Windows. $ [5 @/ l6 i$ X% s- J. E, d& `
Language : Good English verbal skills plus reading/writing for documentation. / n1 W9 A3 K8 b, L7 `+ v2 U6 g
Spirit : Good team spirit, professional, motivated and eager to learn combined with natural curiosity "to discover", "to know" and an attitude "to fix a problem". 4 @! s6 p8 s3 n* C$ w* P9 E: n1 o) N5 A. d5 Y2 E$ e
能者與意者請email研發簡歷與chip123聯絡。作者: mister_liu 時間: 2011-7-22 12:07 PM
招聘公司：A famous IC company # _, U4 i" ^) O! N6 y0 b& W+ j招聘岗位：Firmware Verification Engineer (Enterprise & Storage Division)$ e5 ^) B+ w" u4 g0 Q9 ]
工作地点：Shanghai% C: l, P0 U/ f j( a5 Y' ^0 Q
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岗位描述Job description:9 t" A# e8 h8 O9 C' r) }
As a Firmware verification engineer, you will join a rapidly growing team of professionals in the development and verification of real-time firmware for storage ASICs. Your initial responsibilities will include, but are not limited to the following: 7 X# P, q3 M" A) f5 P- b$ p( v Collaborate with global and local teams to verify the full storage system solution.1 k5 N4 I) x2 b t* E
Analyze technical requirements and Firmware designs to create the verification test plan / m/ A* Z5 Q5 \" X4 Y
Develop the test cases including both system level and to interfaces. * j7 ^- a4 G" F% ~# T/ v1 r
Execute the test cases and debug the issues found as well as provide comprehensive analysis. W. i+ ]# g6 ]7 n3 L7 t0 b
Log bugs found to tracking system and follow up till the end of life 3 H, m. R. p4 h& \1 s Participate in specification, design and implementation review with peers.% f) U! _) m. x, n5 f6 j( y
Use of storage testers, analyzer and other debug tools. d4 W* Z( `# }7 x5 C- R
Write and review engineering documentations& g! |6 ?: r9 _8 z/ B x
4 w$ `/ p& |4 J% K$ @职位要求Qualification:& v' |$ @+ v" q1 A
Master or Bachelor’s degree in Electrical Engineering or Computer Science / e; c' \; K6 j 3+years of Firmware development or test experience 9 l! A8 P# z" w/ ~ C language programming and debugging) f) Y6 f$ O1 _: X. i) ]5 P
Skills of script language programming, such as Perl, Tcl/Tk, or similar! H! y/ y! r( U! h2 F6 x" C4 x
Solid knowledge on Linux kernel or device driver or tools. . n2 P; A$ ~! e" s( G" r, U0 V Master test process, and experience on test tools and test cases development 9 }; j0 m% F2 o4 [( A Familiar with storage specifications, especially SCSI, SAS, SATA, and PCI Express are plus.作者: mister_liu 時間: 2011-7-22 12:16 PM
招聘公司：A famous IC company * W) M4 f3 H4 L3 \3 i; ]6 G5 r5 Z招聘岗位：IC logic design engineer( u. }/ s r* a8 ~2 b! }5 S
工作地点：shanghai / T$ g# ^( Y# P' y" m: A/ X3 M* u$ }, _6 w8 ~7 t
岗位描述：7 \- l; W3 i+ [7 `, s
Job Duties: Micro-architecture design, RTL coding, simulation and verification of the assigned graphics block; should be also responsible for the synthesis and timing check of the block. ( J( z3 a, n! I + s. _9 v5 U4 p8 u- Q3 ? H职位要求：Qualifications: (Educations, Experience, etc.): ' ^ A# l6 G: L2 s1.Education: Master degree or above, major in Micro-electronic,EE, CS or related.9 \% z& H; H2 x3 W; \+ E
2.Experience: Have experience on SOC chip design. 5 u6 }! _* Z6 I, h, U3.Knowledge of/Skills and Abilities * H: N, [: L. K3 s0 P·Be familiar with IC logic design flow; ) N4 I3 i$ t' h1 ^$ U- U·Have good skill in RTL coding, simulation, synthesis and static timing analysis;3 E% Y, l# }7 s* y
·Have strong hardware knowledge of computer architecture, Know-how in computer graphics is preferred;4 z3 K, K9 g! ^2 x& t+ W
·GFX Chip design experience will be a good pls.作者: ranica 時間: 2011-8-3 02:48 PM
招聘公司：a top 15 semiconductor company ( Z0 x; w& |, r8 x. n/ G R& f招聘岗位：Senior Digital Design Verification Engineer/ Z1 J" C2 R6 I
工作地点：Beijing 8 [$ x( S6 y z2 a9 x. i / P$ {3 P: |) `; O岗位描述：; f: ^$ F' n# r) \; f% F
Job Description Responsibility: The responsibilities include but not limited to: 1. Leading the high efficient verification platform development for application specific digital processor system and the whole chip digital system. 2. Leading the high efficient mixed signal verification platform development for mixed signal chips. 3. Work together with local and US team to define the verification strategy, test plan and quality benchmark. 4. Work together with local and US team for system validation. 5. Digital micro-architecture design, RTL design and implementation.+ C0 l* Z; T# P3 D$ B% O3 d% f# S
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职位要求：1 y {+ C. l3 i6 W; |' Y9 H, x
Requirement: 1. MSEE or PhD in EE or microelectronics or computer engineering. 2. 3 year+ experience for MSEE and 1 year+ for PHD on digital verification, RTL related design and implementation. 3. Proficient in SystemVerilog and advanced verification platform development (VMM/OVM/UVM/etc.). 4. Be familiar with SoC design and verification methodology is preferred. 5. Be familiar with digital signal processing for image processing or communication is preferred. 7. Good spoken and written English. 8. Self motivation, result oriented, good team work and communication skills.作者: ranica 時間: 2011-8-3 02:49 PM
招聘公司：A famous IC company ; b5 v+ t \& ]" [& V& d招聘岗位：Design Verification Engineer, Staff 4 K- b! V9 `, |. c5 f工作地点：Shanghai ( W, |) U4 Y: [- G* E6 R9 J3 B: v5 P4 }5 D0 m$ a6 C/ P0 J# ^' |) e
岗位描述： 0 z( D0 V- i' r4 m, L' u6 pJob Function This DV Manager will be part of a team working on the future integration of complex SOC and switching product. The successful candidate will play a key role in driving many of the key DV architectural and in depth technical aspects of various projects and perform the following duties: - A multidisciplinary function, working in close collaboration with the design engineering teams and managers and directors on the various efforts involved in the definition and implementation of various projects and scoping development efforts and project schedules. - Responsible for the overall chip verification, in addition to the possibility of direct responsibility for the architecture of specific IP blocks or functions, depending on any specific area of expertise the candidate might have. - Interacting with and guiding a wide variety of internal and external design verification development teams, DV methodology, silicon IP and tool vendors. - Work with senior management, architects, and the design and DV teams across sites to contribute in definition of ASIC products specifications, feature definition and architecture.作者: ranica 時間: 2011-8-3 02:49 PM
职位要求： ( N2 `4 z3 G6 U+ ^" \; s+ lSkills/Experience - 10+ working experience in the field of design verification, experience in networking or switching design is a big plus. - 3+ years as DV technical lead/architect or manager position. - Proven experience of the latest design verification methodology such as OVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation, formal checkings, power verification, modern design verification tools and languages (e.g. PSL/SVA, SystemC++, SystemVerilog, Vera, Specman, simulation systems) - In depth experience in use of SystemVerilog and OVM to drive testbench is highly desirable - In depth knowledge of ASIC design fundamentals from RTL to GDS including DFT verification. - Experience in power verification is a plus. - Proven debugging and problem analysis skills. - Strong documentation and communication skills. - Good people and project management skills including scheduling, resource allocation, risk assessment, matrix management, and process development and organized and methodical with proven ability to plan and execute project. - Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia - Flexible in terms of responsibilities and hours. Education Requirements MSEE or PHD in EE or CS作者: ranica 時間: 2011-8-10 05:34 PM
招聘公司：A famous IC company : K- ?. i' o6 K% g" `招聘岗位：Lead SW Integration and Verification Engineer3 v0 S) K9 _' Y
工作地点：Shanghai 3 ^ w. V8 {) V , U& w2 ?/ L- V( j6 V岗位描述： 4 ~5 M0 J- i+ j' tJob Description S/W Integration and Verification engineers will be responsible primarily for defining the requirements for system and software test based upon system requirements specifications and preparing for detailed, comprehensive test procedures. Key responsibilities will include validation of S/W package as well as integration with GUI, DLL, COM, and device driver. Applicant must be comfortable with quickly learning new technologies, have strong design and problem solving skills and must be a team player. 3 S9 D* T$ v* ^5 V9 @7 v4 O8 e: e8 f+ }- e- h+ j7 B, o# ]
职位要求：( A' s( U5 Z" d
Required Skills - Bachelor or above of Software / Computer Science or equivalent experience. - Minimum of 4 years of SW verification expereicne or equivalent. - Strong knowledge of at least 2 of the following scripting languages such as Perl, Python, VB script, DOS batch file, or Unix shell script. - Must be proficient in authoring and updating test plans with raw data, and summarizing results with simple spreadsheets or complex/custom data analysis tools. - Experience in each of the major testing types comprising a test cycle including functional, system/integration, regression and error handling. - Create, maintain and execute automated tests using script languages. - Proficiency with scripting languages, compiling, and debugging builds for C/C++ applications. - Strong verbal and written communication skills. - Exposure to the entire software development life cycle. - Utilization source control tools such as Visual Source Safe to establish proper version control of automation scripts and to build the S/W package for integration. - Understanding TCP/IP Network stack is a plus. - HTML, SNMP, or XML Experience is a plus.作者: ranica 時間: 2011-8-19 02:13 PM
招聘公司：A famous American IC company ( U$ D1 ]% }* K8 O( y( ]4 A招聘岗位：Sr. Staff ASIC Verification Engineer / SOC Verification Lead7 ~ W9 p% N7 s, L# f( m; F
工作地点：Shanghai6 K V; i5 A2 Y/ [
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岗位描述：7 V, a( a; [0 E* ^; v& C
Job Description:. V& Z8 f* _7 n' D
As a core member of a XX China SOC development team, primary responsibility will be verification environment development and verification planning and executing. Lead the verification group to accomplish SOC project verification tasks. - u4 z H( W. y5 [. C: f . \5 G Q2 Z+ Q3 Z( tSummary of Duties/Responsibilities: 0 u: d7 G: h$ p9 M% R( E1 C! ^· SOC verification requirements analysis and planning, o, P* X1 w3 p/ Y
· Architect and build OVM based test environment for efficient and flexible IP level and SOC full chip verification ! v% k1 P- S; N) A9 s; n, o· Create test plan, and lead the verification organization to implement the verification tasks* F4 l: d) O; W& d+ N; g
· Design coverage metrics and verification reporting system 1 U: @9 j" O- V8 P6 w) D· Coordinate debug efforts to achieve IPs and full chip functionality L% B6 C5 q, j; ~6 x) R: \· Documentation of verification, organize/participate in verification/design reviews作者: ranica 時間: 2011-8-19 02:14 PM
职位要求：Job Requirements: 4 U. d! j( O& ?$ t4 }5 D7 k· Excellent English and Mandarin skills & D( D( [' b1 E9 r8 z3 Y- F
· Takes initiative and sets high goals, smart and confident 2 K7 H" h& j! s· Self starter & ability to work in a team environment as an individual contributor / m. T/ ]2 }9 e; ~7 l- Q· Tracking record of planning and delivering successful verification projects 2 @' a& k6 W8 a· Expert of advanced verification methodology, like OVM, VMM4 O, n1 h- u. r2 [+ U8 S2 h6 P# G
· Ability to test silicon using logic analyzers, oscilloscopes, and other common laboratory equipment is a plus. : u. j3 m. \# w- a" T. l+ @1 a
· Thoroughly understand SOC development flow, solid knowledge of semiconductor technology 0 w" c) d( G1 x/ [9 p ( y/ ?0 }7 D, xEducation & Work Experience: ; _+ u* A* ~% w; \6 _- K6 U5 S· 6+ years of verification environment development & SOC verification 1 x' s+ S' a9 R( i· 2+ years of team/project management experience; 6 Z( S6 C6 _1 t. o$ u# p· Expert in System Verilog and OVM or VMM verification methodology ' }& f: n4 X. L: p% g: A4 Z· Proficiency in Perl, Tcl, Tk, C/C++, Verilog, System Verilog languages 6 I0 V! V; f. E6 B8 S# @ t
· Master's Degree or above in EE/CE % g7 K3 F5 K, t, P% z8 P 7 @* y) R* u) e# GBenefits:: u$ k# ~" l8 w" r
· Competitive salary ; x% z/ b2 B5 W! C. ]) E$ U: W
· Stock options & C' g% p$ q. `0 C5 ^2 F. Z· Excellent medical insurance plan ; F+ p5 |) Y B- v1 l) P
· New product design bonus 1 k5 G- u3 S6 w$ j D
· Extensive training programs covering technology / management skills作者: ranica 時間: 2011-9-8 10:54 AM
招聘公司：A famous European IC company 7 B& {$ _5 D( H H O7 y招聘岗位：Senior Digital Design Engineer+ T4 I7 R# K" I
工作地点：Shanghai" t- x* X* U& H+ v" A: V- m
6 O3 |* v5 \( v岗位描述： , u4 }' \# k, o( V! g- Define specifications in cooperation with international teams - Design and verify digital circuits for mixed-signal application - FPGA-based verification of digital circuits - Estimation of efforts and schedules for design projects - Close cooperation and interaction with international teams: H$ M' ?/ z( J$ o, z3 e& I
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职位要求： 3 X, {9 R, F* x7 l) [* J% a5 R. s6 F- YRequirements: - Bachelor or master degree in Electronics, Communications, - Computer Engineering or equivalent, 2+ years - Strong background in digital design and verification - Experience in working with FPGAs - Flexibility and open-mindedness; Self motivated, excellent communication skills and a real team player - English written and verbal; - Willingness to work and interact in international teams作者: ranica 時間: 2011-9-8 11:00 AM
招聘公司：A famous IC company" H# b3 x M* W1 T" } P6 X( N$ P
招聘岗位：Senior / Staff ASIC DFT engineer (MCE ASIC) ; X3 b' G' g1 W' e2 e9 v/ E _0 d+ g# k工作地点：Shanghai ! D5 z" q$ _5 G1 L: @5 K) [& Q3 Z2 j0 I+ s8 z* X2 v
岗位描述： ; w0 b3 q+ e, I2 qDescription: Sr. / Staff ASIC DFT design engineer Focus on DFT design & debugging of leading-edge large SoC. & U$ y. T8 A9 t; u7 I, b9 P
- T7 J' q4 y2 _# s. p职位要求： - q; `# y& x) d" V& wQualifications: 1. BS (MS preferred) in microelectronics, electrical engineering or equivalent with 3+ years of DFT design experience, preferably with large SoC chips. 2. Handy experience on scan, mbist, boundary scan, ATPG and analog DFT, with Mentor/Synopsys/Syntest tools and RTL/gate simulation. 3. RTL design and STA experience is a strong plus. 4. ATE tester experience is a plus. 5. Must be able to communicate in both written and spoken English 6. Good team work spirit and communication skill.作者: ranica 時間: 2011-9-22 03:20 PM
招聘公司：A famous IC company 6 }" Z+ a3 ^5 {招聘岗位：Senior Digital IC Design Engineer (DFT)& E2 W. O5 j+ M
工作地点：Shanghai 0 p) C% A& B/ F. {6 O# X, c7 o5 Y: f
岗位描述：( i; }- x7 x9 X' ?# ~
Job Description: • Participate in SoC level DFT architecture definition • Implement DFT design for the SoC chips, cooperating with design team • Develop the high coverage and cost effective test patterns. • Generate and verify DFT patterns. • Evaluate and establish advanced DFT tools and flow. • Support other teams for DFT related problems # A& Z% V/ E" w# @9 ]: X8 O7 i
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Requirements • B.Sc. degree or above in Semiconductor, Electronics Engineering areas • 2 year or above DFT or related design experience in industry • Good knowledge of IC design flow, including coding, simulation, verification, synthesis and STA. • Be skilled in the main EDA tools for design and simulation such as ncsim, RC/DC, Formality/LEC and PT. • Be familiar with Synopsys/Mentor DFT flow and tools • Proficient in Verilog/VHDL language. • Be familiar with shell/TCL/Perl grogram. • Good communication skill, will have frequent communication with foreign teams. • Good written and spoken English is mandatory作者: ranica 時間: 2011-9-22 03:21 PM
招聘公司：a top 15 semiconductor company 7 @& n( l8 v! \9 k招聘岗位：Experienced Digital Designer1 p! R: B. ~8 e8 n1 g
工作地点：Beijing2 O& m4 n+ ]' Q1 z4 q
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岗位描述： % {: \# W' x$ l8 j# d4 o6 SResponsibility: Participate in mix-signal IC development high speed mix signal products, working with multi-site engineers on different functions such as analog design, application, product evaluation and layout. The candidate is expected to contribute to signal chain understanding/partition, design, verification, synthesis, timing and power analysis. And he/she is also required be able to understand input from application engineers to translate real word issues to design requirements. Some basic lab skill to work with product evaluation engineers and understand real silicon issue is also desired. 4 N& E% s' m# m5 L5 D
4 d9 |; Y/ M- W, \& A' |( o0 Q9 g职位要求： 0 o$ k3 M; B0 `8 @+ kRequirement: MSEE or PHD in EE related majors 4-10 years working experience on RTL related design, verification and physical implementation for FPGA or ASIC. Be able to working with team mates to handel digital design from product concept to GDSII on each key task node, and have expereince on real silicon debug and probe. The candidate should have basic idea on sampling theory and digital signal processing. Basic analog understanding with real mixed signal ASIC experience is preferred. High speed design experience is a good plus but not a must. Self motivation, result oriented, good team work and communication skills. Good spoken and written English Supervision skill and project leader expereince is also required.作者: ranica 時間: 2011-12-2 12:22 PM
A famous IC company ( [: q% R# V6 C' n招聘岗位：Senior/Staff SoC Verification Engineer ~5 Z" O+ Q% b, V" t4 T! A
工作地点：Beijing% E7 d4 s |- B5 r
P+ @) k- z% h/ V/ m) x2 R( K岗位描述：0 g+ C) p# i& k& F K! M8 ?+ H; K, e3 T
4 o/ p Z6 j k9 v8 m a8 l) ^Responsibilities: Work with SoC architect (team) in design exploration and test cases definition. Build and maintain SoC chip level verification environment/testbench based on multiple IP level testbenches. Develop SoC level test cases based on architecture and functional specs and work closely with IP providers. Be responsible for a complete simulation coverage and verification closure at SoC level. Make the verification plan and commit to the time and quality objectives. Conduct RTL simulation and sign-off functional and timing simulation on back-annotated netlist. Work closely with the SoC architecture, IP design/verification, and validation teams in solving design and implementation problems. Strictly follow defined verification flow and rules. Report to IC dept. manager and project manager.作者: ranica 時間: 2011-12-2 12:22 PM
职位要求： % K6 w3 e4 m. PRequirements: Master or higher degree in Electrical Engineering or Computer Engineering. At least 5 years experience in IP/SoC function verification. Experience in portable device or wireless communication device IC design or verification is a plus. Solid verification skills and an expert in HDL language and using logic simulator e.g NCSIM. Hands on experience in verification language such as SystemVerilog or Specman E. Well understand OVM/UVM methodology. Experience in setting up SoC level verification environment is a must for senior position. Added value for those understanding SystemC. Hands on in UNIX environment and scripting language such as Perl and Tcl. Experience in verifying IPs of wireless communication or digital signal processing algorithm is a plus. Knowledge in IC/SoC architecture and design flow. Experience in FPGA prototyping or chip validation is a plus. Good English written skill. Good oral skill is a must for senior position. Ability in quick learning new knowledge and master new skills. Strong debugging and problem solving skills. Ability to handle multi-task at a time and work under tight schedule. Team player, willing to communication, proactive and self-motivated.作者: ranica 時間: 2012-1-6 02:37 PM
招聘公司：A fabless IC design company ' y# J+ W7 ?' J$ V招聘岗位：系统工程师(TCON)3 O2 g1 o9 A9 c) u) a, h* M6 }
工作地点：Beijing. u' Z) a1 z0 [) C) s- n5 a
" d6 _# K# E' x1 \4 g: G职位要求：/ I5 P0 C: {8 M* \; ^' [" F; r
职位需求： 1. 计算机、通信、电子工程类专业，本科及以上学历。英语CET-6级以上水平，良好的英文读写能力； 2. 熟悉LCD 基本知识及相应TCON, driver芯片相关知识，了解通信系统或民用消费类产品的框架结构及应用领域 3. 具备较强的芯片级理解能力，对高速视频接口（LVDS, DVI, HDMI, DP）、数字电视相关芯片有深入的研究或应用，可以很准确的知道芯片的指标含 义和解释； 4. 能够独立调试电源、CPU、FPGA及ASIC芯片，熟练掌握 Cadence或PowerPCB/Powerlog ic等软件，熟知原理图设计，PCB 的布线规则和产品的生产流程； 5. 具备敏锐和快速的反应能力；良好的思维能力、信息收集、分析能力； 6. 良好的团队合作意识和沟通能力； 7. 适应经常出差，勤奋刻苦，爱岗敬业。作者: ranica 時間: 2012-1-6 02:38 PM
招聘公司：A fabless IC design company. }" T/ v2 W# Q
招聘岗位：系统产品经理* U2 Z+ F! u/ g: Y
工作地点：Beijing" h. j. [$ X3 P( ^
, T- X9 Y8 _, k w# [3 s1 ]
岗位描述：9 @3 w0 g# a% @( `
主要职责： 定制芯片的实际应用方案，为客户提供具体系统应用的解决方案，统计芯片在应用中出现的问题并形成改进建议书。 ! i% \2 P2 w- L' w6 x* U) {. b, k4 |4 ]! E3 H
职位要求： # ?" L* C3 V: j$ s8 M ?职位需求： 1. 计算机、通信、电子工程类专业，本科及以上学历。英语CET-4级以上水平，良好的英文读写能力； 2.了解民用消费类产品的框架结构及应用领域； 3. 具备较强的芯片级理解能力，对高速视频接口（LVDS, DVI, HDMI, DP）、数字电视相关芯片有深入的研究或应用，可以很准确的知道芯片的指标含 义和解释； 4. 熟练掌握 Cadence或PowerPCB/Powerlog ic等软件，熟知原理图设计，PCB 的布线规则和产品的生产流程。能够独立调试系统板级硬件； 5. 具备敏锐和快速的反应能力；良好的思维能力、信息收集、分析能力； 6. 良好的团队合作意识和沟通能力； 7. 适应经常出差，勤奋刻苦，爱岗敬业； 8. 具有较强的嵌入式软件编程能力，熟悉LINUX系统的应用。能够独立调试系统系统软件； 9. 具有产品应用及管理经历者优先。作者: ranica 時間: 2012-1-17 09:49 AM
招聘公司：A famous IC company 1 s9 t. G# W% q招聘岗位：SoC System Verification Engineer. k" O+ r2 L5 S5 ^7 s2 L
工作地点：Xi'an4 [5 a* r0 X ~
/ o$ T5 Z j' R& ~4 M( t岗位描述： ( \* A R6 }$ _; j: d& M4 eJob Description: * Defines and develops system validation environment and test suites. * Hardware System Validation of Baseband ICs and peripheral for Mobile Terminals Technical coordination possible depending on experience and skills * Functional verification of the baseband IC and analyze of the occurring problems * Definition and implementation of test cases for the different modules(HW/SW, Low level drivers, Linux drivers) * Lead internal customer support during the evaluation phase * Interface to Concept Engineering Team, Design Team, SW Team作者: ranica 時間: 2012-1-17 09:50 AM
职位要求： 7 m! D# K( G) R& _' X9 qJob Description: * BS. or MS. Degree, MS. preferred, in Electrical / Electronics Engineering or equivalent * Minimum 2 years experience with the following tools/domains are recommended: * Knowledge of Embedded system * ARM Tools (ADS), GCC know how * Script languages (GNU Make, Make, Make File structures) * Debug Tooling Multi-ICE, Lauterbach, OS-aware debugging * RTOS Symbian, Nucleus, Linux or equivalent * Usage of C models (Virtual Prototype) to test Software before silicon availability * Configuration Management (Versioning Tools: ClearCase) * Knowledge of the following cores/architecture concepts are recommended: * ARM 7/9/11/Cortex Series and all controller functions: Interrupt/DMA... * Multimedia concept: JPEG, MPEG, Camera, Display, Multimedia Card Storage devices... * Standard Interfaces (UART, SSC, I2C, USB HS, USB FS, USB HSIC, MIPI HSl, SlimBus, MIPI Unipro¿) * Memory devices (DDR1, DDR2, SDRAM, Mobile RAM, NAND and NOR Flash) * Connectivity functions: WLAN, BlueTooth, GPS, FMR... * Good English, Excellent communication skill and team spirit oriented作者: ranica 時間: 2012-2-20 01:48 PM
招聘公司：A famous IC company$ W/ Z& ]) q6 m( s
招聘岗位：Digital Design Engineer6 S! f9 ~4 N; ?) a0 |) o3 O
工作地点：Beijing ) K3 _* e) z! }2 x% Z2 z0 K- e/ N" d) S& K
岗位描述： & J p: |7 Z$ t9 x+ ~+ }9 m' A. T% wDuties · Digital design, including synthesis, timing simulations, power optimization, DFT · Mixed signal design; and verification · Define, develop, and implement characterization, test plans, test vector generation · Work with other division test groups inside/outside FSC to identify possible co-operative opportunities to optimize test solution · Work on the design of analog blocks like voltage regulators, I/O buffer, output drivers, voltage references, oscillators · Work with product definition; characterization, and test engineers in the full product development flow; Work with application & test engineers to define optimal design and characterization solutions, based on design objectives · Layout floor planning, including P&R, DRC, LVS, and LPE 6 G0 N/ _6 k; s( a. @) a* U8 u y7 p0 r* S. x6 Y
职位要求： ) ] x2 Q7 B- `) _7 Q$ S5 mRequirements · Minimum 3 years direct digital IC design experience · Minimum 3-5 years direct mixed signal IC design experience · CMOS mixed signal circuit design and proficiency with industry standard design tools and Verilog/VHDL · Knowledge in CMOS/BiCMOS Analog circuit design Experience in Cadence IC Design tool set, simulation, verification · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus Team-based, cross-functional organizational structure experience preferred · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills作者: ranica 時間: 2012-2-20 01:49 PM
招聘公司：A famous IC company! O- |2 t0 B; g3 U0 D% q3 _& {
招聘岗位：Sr. Design Engineer' }1 J9 i5 H* C# M
工作地点：Shanghai、Beijing6 F+ z' o9 W9 _. t1 E5 J9 Z
1 O4 W" o; V+ M; h+ v% w
岗位描述：0 {4 z v9 ?( H0 ?& r9 `1 v
Duties · Analog IC circuit design, simulation and verification · Design analog products and blocks such as high current or high capacitive load output drivers, operational amplifier, comparator, voltage reference, oscillator, error amplifier, voltage regulator etc. · Design of the switching power IC, DC-DC converters, for mobile/portal application · Evaluation, simulation and analysis of power architectures and circuit topologies · IC layout including floor planning, DRC, LVS, and LPE · Work with application and testing engineers to define optimal characterization and testing solution · Work with product definers and product engineers in full product development flow: Q/ K, w ?$ _/ `& h! J2 s( j/ }
8 h% a: l& A' t: k职位要求： ) ~$ a$ x/ `# v5 j9 C2 n s5 vRequirements · Minimum 5 years direct DC-DC IC design experience, with MSEE or above degree · Strong knowledge in analog CMOS and Bipolar IC design · Working direct experience with switching power supplies, DC-DC converters, Battery charger, and their various topologies · Theoretical understanding of the power electronics, switching power supply topologies · Prior experience with power management related IC design a strong plus · Knowledge in analog IC layout · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills作者: ranica 時間: 2012-3-19 03:10 PM
招聘公司：a top 15 semiconductor company 2 R' w2 ^' ^. }+ [0 P& V$ S1 ^招聘岗位：Product Engineer 4 R! d6 u D6 t2 H5 h, t工作地点：Beijing * @. P# @! d) k: a# L# K1 v9 e& A- F* X; c, {" ?: L8 [# ^! o
岗位描述： ( y, a ^- O0 ]- Design database verification by simulation and on FPGA - Chip function evaluation - Develop test firmware and tools (Hardware and Software) - Develop evaluation board - Cooperate to debug chip issues - Customer support • Assist with customers’ issues • Visit customers and provide on-site support • Build up demo system5 A* ^$ U+ h) i$ c9 ~
) R1 P& n; d7 [# ?职位要求：& D0 e; V7 k. y1 ^
- BSEE or above with minimum 3 years communication system experience - Familiar with Verilog. Has digital design experience with Verilog in real project - Minimum 3 years FPGA working experience, including code writing, timing analysis, debug - Familiar with at least one of schematic and PCB layout tools - Excellent English skill will be required. - Strong inter-personal, teamwork and communicational skills作者: ranica 時間: 2012-4-12 10:21 AM 標題: Staff Engineer for Digital MAC Design 客户 A famous IC company; i7 A8 L4 J$ p& {; Y8 Q
地点 Shanghai x; K7 w1 G, q$ ?) A# m9 @; L# E8 K
职位描述 ) l( y& _: v& o4 ?; c+ I. CWe are looking for a person to join a design team to execute a state-of-the-art IC design project in the wireless communication field. Candidate must be familiar with digital IC design flow with a proven record of design and verification of a complex design project that led to successful silicon. Proficiency in Verilog is required.1 G! F7 n, Y4 G+ q! @) E* \# _2 N
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职位要求 * E! q1 o6 y% j& UExperience in the following areas of expertise is desired: + f- ?+ X0 Z) P1 m( _Wireless media access control (MAC) design experience would be highly desirable ( P8 _" [7 z, `6 z6 {Knowledge of TCP/IP and DMA Offload Engine design experience will be a plus. v: j, C: _1 n& S
RTL design, verification, and chip integration 0 g8 x- b% h) s& R ]3 A9 _; P- xExperience in the following is beneficial but not necessary requirement: + c( W( ~4 z$ M3 u% t/ ECommunication systems and RF systems * P; Q! {0 O1 L+ bFamiliarity with wireless communication systems and standards (802.11b/g/n and WiGig) & @0 b, \/ ]/ S# u6 u7 X }( f$ ?Knowledge of interface protocols such as PCI/PCIe would be a plus8 B1 f: t' g% x3 a& ?8 Z: p9 z
FPGA design flow, testing, and emulation bringup * q F+ V0 }. A8 m9 z! O, G+ K; h ; G3 [3 ?9 O6 k6 aOther requirements: 7 j$ y! M, V; }4 w+ T8 b& M+ j; sFamiliar with design and verification languages, EDA tools and ASIC/SOC design methodology ' A( z: k9 x. ?' WGood script language skill, such as Perl, Tcl and Shell 9 |+ A1 g8 Z4 G4 }7 k. X5 E) YGood written and oral communication skills in English ; A9 X" |3 T/ v! p1 ~Good Team player, H8 y0 K# h N# Y
Candidates must have MSEE degree with at least 5 years of experience作者: ranica 時間: 2012-4-18 05:28 PM 標題: 高级ASIC设计工程师 招聘公司：A famous IC company b7 H/ J1 N* n8 u0 L+ ^招聘岗位：高级ASIC设计工程师 ( u3 l" `4 t/ R5 W, h3 x工作地点：Shanghai. ?! t/ `" x+ R8 J, Q0 J
* W8 Y3 u/ C% e* Z: k+ F
岗位描述：* A+ O+ I% c1 m
1、定义设计模块结构并编写芯片设计规范； 2、使用VHDL/Verilog编写逻辑模块的RTL代码； 3、编写测试向量对模块进行仿真验证； 4、在FPGA平台上进行芯片级的测试验证； 5、进行模块级的芯片综合与时序分析； 6、编写完整的设计和验证报告。 4 w! m: q) s2 i) I) t% |' s3 ]* [; R/ Q
职位要求：7 i: L) k; s1 ^
1、具有电子或通信工程类硕士以上学历； 2、 熟练运用Verilog/VHDL进行芯片前端设计，熟练运用设计仿真综合和测试工具，如quartus，Xilinx，modelsim，nc，debussy，逻辑分析仪，信道仿真设备等； 3、深刻理解数字电路设计和时序分析方法，并拥有故障定位和解决问题的能力； 4、深刻理解通信原理、数字信号处理等基础知识，熟悉无线通信原理与常用算法； 5、具有3年以上芯片设计经验，拥有无线通信物理层开发项目（如DTMB、CMMB、DVB、3G, LTE等）经验者优先； 6、工作认真严谨，积极上进； 7、良好的团队合作意识和沟通能力。作者: ranica 時間: 2013-10-30 02:16 PM
Verification Engineer7 q: N7 q- i4 Q/ M& _# a
! G3 o3 C: p7 v: R% r3 X' S公 司：A famous IC company$ R4 Y3 F+ ]" h. x! Y
工作地点：上海& s0 i9 j" }8 Z9 G" M. ^) z% x
2 {+ m* e" N' h
The Role: 9 w1 J+ N' ?" b* m, N. L/ W, N· ASIC verification - W! G$ s/ D% x& h· Work closely with the California teams j/ j# ~2 V; n! O7 _2 V" \
· Support chip tape out and bring up ! X' i6 x( m' X* r( H
+ C; a7 ? x8 \% Z
Requirements: 6 k8 Y( w( R8 z
· 3+ years experience in ASIC Verification ( ~- R. I( \. v0 V: {6 A· BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired 0 q2 m1 }6 n% o0 ]
· System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification $ A5 z: | ]- U( X% T* E· Very familiar with verification languages – Verilog, System-Verilog, and VMM 4 q; ^! o4 h b4 U: D8 z: c" N' a
· Test plan and test case documentation 2 s( U) l# Q% R5 }
· Functional coverage and code coverage analysis ) f* T! O5 L& _; s" Y w/ d. W
· Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc. $ @$ _; c( L& L2 Z# r
· Experience verifying interfaces such as PCIe, Ethernet, DDR, USB ; ^4 @4 A5 d9 e6 }" i, y· Working knowledge of networking protocols 802.3 and 802.11, especially Medium Access Control and TCP/IP & h' y0 E5 z8 X* l· Working knowledge of C programming language ' j# X6 d9 i1 `! x a7 F· Must be familiar with the ASIC verification flow from feature identification to test bench development and through final tape out sign-off $ f, Q7 A+ M( j+ }6 D# L6 Z9 P
· FPGA emulation experience a plus 3 @. B) R: Z4 y
· Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging作者: ranica 時間: 2013-11-13 02:39 PM
ASIC Digital Verification Engineer% j: e& G5 G# b* m7 c1 H
公 司：A mobile chipset semiconductor company 4 _, \3 h7 W+ m) ^工作地点：上海' j& P( n, {0 c
5 a X' n5 t2 {# WResponsibilities: % c) E3 k( h( d! I" v6 L+ I
Make verification plan for one module or whole chip. ; f8 o5 S+ G B% A i7 I! u
Build up and maintain module-level and chip-level verification environment 3 o7 H; I+ x# i e4 Y/ r3 ] Verify ASIC digital design based on case list, and output verification report. 1 |! @$ i6 a; R7 H Also responsible for lint checking and formal verification. ; U- y1 C' \; C e! K7 ]7 V' n + A; @7 X( R+ }4 v3 |7 \Qualifications: $ `. C' G9 h, y0 d% Y1 e4 \6 _
Proficiency in logic verification. 6 Z" M+ X8 Y3 C' R) q! m4 z+ `
Experience with Verilog logic design language. % S$ j* J ^- M9 m" R. A J, H( h
Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language. 3 \& V6 F' q/ r; f7 |! V& W- I Experience with UNIX/Linux simulation tools such as IUS or VCS. # M: r5 @& L) {) k6 E Experience with C and C++ is a plus. 0 z/ j3 ~: u1 ~8 o Experience with C_SHELL, TCL or PERL is a plus. 9 {5 K6 K( r a s) q0 S) C
Experience with UVM, OVM or VMM is a plus. - k& m+ S0 e4 H3 ? r0 h8 g! |- R
Good knowledge of SOC design is a plus. & a( W- l2 ?, N r; R2 U
Good knowledge of software design is a plus. 2 F6 e% z( v1 g W1 G. L
Self-motivated and good team player. ' c: |$ ]- z1 Z/ Q% S- w4 w
MSEE or BSEE with 2+ years.作者: tk02561 時間: 2014-1-16 10:26 AM
Hardware Applications Engineer–Graphics ; G1 h% O8 I# B t* K; N5 {- R公 司：A famous IC company B. O6 B S0 i1 R" i) N
工作地点：上海 6 E6 r j- F* Y& U# n$ i r$ E& x6 L4 D9 L! u$ X: ^' d
Desirable 5 i( D( A) K" {% r8 A3 r
Strong understanding of microprocessors $ A$ x1 W( h& }& N3 \' rA good understanding of the interaction between software and hardware . L Z/ i9 |' ?/ L2 o0 ^Understanding of FPGA or ASIC implementation flows (synthesis, scan insertion, layout) " ?0 D/ J Q! V- a+ i2 [. BC/C++, assembler coding or other programming skills. ! g: a% ~6 H! T/ T6 E2 jKnowledge of GPU or graphics processing specification, like OpenGLES, Direct-X, is preferred ; r @2 Z$ W, J8 X" u9 F+ A3 q& G. U5 F4 q
Job Requirements：作者: tk02561 時間: 2014-1-16 10:26 AM
Education 2 g6 z8 B8 i- `* O$ o7 @: K
Good university degree, in Computer Science or Electronics Engineering ideally, although other science graduates would be considered if they have relevant experience. ; g9 U6 Y' T, ?4 F 2 C5 A0 Y% a- o/ @- R4 J3 [! z
Experience 7 U% d7 o% D$ v0 ~7 U
Minimum of 4 years industrial experience : b3 x6 k5 ^$ P6 [# h8 P# v3 a6 \Experience or knowledge of FPGA or ASIC design, simulation and/or verification techniques, including RTL coding and simulation, in Verilog or VHDL x5 S/ a; B) u7 p6 o/ k4 ?
Experience in integrating SoC peripherals $ @6 {0 e6 Z) e* n. g1 Z
Experience of interacting with colleagues outside of China # |4 Y! x/ p, _! N+ q8 }2 ^* T# B1 H
Professional experience of customer and sales interaction # ?5 a" T, l# kDemonstrable experience of problem solving and debug skills : M+ Y6 a1 e* I# n- X" q M% `- }. {2 @8 i/ V& Z* a
Personal Requirements / l& A: g& h QMust have excellent written and verbal communication skills with both colleagues and customers, including good written and spoken English # b& T% ^# B. ?! mMust be proactive in obtaining engineering or management input, in order to complete project and internal tasks in a timely and accurate manner 0 Y b# R( H" u' `# d0 B! OMust have the desire and ability to solve problems quickly " c3 x3 _0 M& A6 M+ g* h/ Y+ ]Must be enthusiastic and well driven % M3 n) W1 Y) E% q# {Must be able to schedule own workload and plan tasks – based on both internal and customer requirements. ' @$ M& C4 e" H: W' E' Z7 TMust have good inter-personal skills, and be able to work well within a team; especially when under pressure N9 Y" s* w+ V' {4 x
Must be willing to be flexible and accept new challenges ) D/ x5 t) B% K" I6 q( SMust be able to travel on a regular basis, both to give customer training and also for internal business reasons.作者: ranica 時間: 2014-1-23 08:54 AM
Senior Digital Design Engineer 9 U; Z" N! i3 F公 司：A leading semiconductor company0 {7 c+ ^- k; {" }
工作地点：香港 / k+ m0 C2 |- ~7 Y * r% e! R$ `3 U$ rJob Responsibilities: + N4 o: i* @/ h7 y Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis 4 h& ~- R% v, E$ h% x Develop verification environment and coverage closure 5 l2 i* j; [$ Q7 r Support wafer level testing and silicon evaluation 3 M' ?) z" V2 C9 e. f$ {' C Prepare technical documents 2 s! u% y5 o( T; L2 w9 B5 Y3 |. c3 ]% J2 N6 {2 H" n9 v+ C8 i" A) P) f: B
Job Requirements: ' S1 C5 q/ _" d) r5 b2 o
B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage+ ^0 b. |7 Z I& f* N. _
5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations $ _7 U( a" E' B Knowledge of SoC and embedded system. 7 Y5 k! l! I8 O Knowledge of scripting languages such as Perl, TCL and Make ( n: v6 n3 ]; C; m8 a Candidate with less experience will be considered as Digital Design Engineer作者: ranica 時間: 2014-3-6 02:29 PM
数字IC验证工程师 9 j, L. P7 f% }) A8 ?" W# S3 Y公 司：A famous IC company 8 L" M( U. @$ z* B工作地点：上海 - h- \; @5 l' k$ T, ^3 r ) j& X% t# Z1 ]岗位职责： 5 [# l9 Y! B1 M1、负责整个团队验证平台的搭建、维护 0 Y7 v# F. M: @
2、先进验证方法和验证平台的评估、导入 1 C, T. ~) _0 p k3 W& T2 p
3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。 & Q1 k z4 o% X6 G. f# D3 s' A5 i: V( g& B2 A4 V- a: J
职位要求： 3 u& Q O) A: l1、大学本科及以上学历，电子、通信、计算机或微电子专业； ( p/ ?% {6 C2 N5 X- B' s. N2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础； ' Y4 f! R9 U. }5 L) A6 A+ L3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等； 4 \0 c5 Q6 N7 Z5 m
3、有1~2年芯片验证的相关工作经验； ; t$ i c6 b6 D. C2 e5 @5 y: f4、具有较强的学习能力、沟通能力和良好的团队合作精神； 4 h# L7 X5 q, h5、有基于ARM处理器的SOC芯片验证经验者优先考虑。作者: jcase 時間: 2014-3-11 01:15 PM
数字IC验证工程师 % w! `) u$ `0 A! J& U公 司：A famous IC company . E. A1 _. _! |: t& u工作地点：上海 ) s8 w& v4 l- w: I5 f3 U9 m. X: Z9 e. Z/ [. V, y* d
岗位职责： * |1 S7 j6 ^4 N7 o; d
1、负责整个团队验证平台的搭建、维护 8 Q; E- Z, [3 q; {2、先进验证方法和验证平台的评估、导入 - U* `3 q7 O! m9 n
3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。 & t3 z% Y1 Z; `# O ' {* X# C7 t$ |" k) _. f2 M. B职位要求： 7 n. \8 a& s3 U: k F" @% p
1、大学本科及以上学历，电子、通信、计算机或微电子专业； 7 k/ I. Z! K+ l2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础； & y0 V! Z! d$ o0 P' y3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等； 7 t. H# D1 G* p+ u/ @- M
3、有1~2年芯片验证的相关工作经验； 8 B! `- [. B( ~2 x3 p$ u& {& t4、具有较强的学习能力、沟通能力和良好的团队合作精神； % T6 a2 L: k" G' m, S( K8 _
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。作者: ranica 時間: 2014-3-28 01:07 PM
Senior Digital Design Engineer 1 z% P8 d% m( f; R公 司：A famous European IC company. q: ^; M M7 M- _
工作地点：上海0 |% g2 X f2 I4 q% g- [. J
. {7 \# R6 _/ o' S, y |
Job description ' E) C9 o' f- }4 r* D0 a. k- define system partitioning of s/c circuits and system 4 u1 V" z& ^, s' C" J. X; Z- define HW/SW co-partitioning 5 H7 F! f' r; Y, }' X- provide technical feasibilities based on system simulation and/or FPGA based demonstrator , M, H3 R9 m/ Y/ e; D F9 p/ T- propose new technical solutions on s/c and system level % h& h* y( Z& L; F- n2 q3 T
- design digital part of mixed signal (smart power) ASICs ( r1 F: I+ _! B) q; y* {- close cooperation and interaction with international teams : I& b9 ~) D6 r+ D- coach junior engineers 9 b" R8 _& A& g) u! Z2 L
9 l+ T1 s7 c( Q1 c& D
Required knowledge competencies and attributes 7 f7 X$ O5 l6 q7 E' m- master degree in microelectronic circuits or systems, Communications, Computer Engineering (or equivalent) / D/ X3 b" {4 K3 D# P5 x- > 5ys experience in digital design 8 H* |" J* t S8 ]. f2 K) B' w- good understanding of ASIC mixed signal flow (Cadence based) 0 I. u( Y* X9 n. P, q
- strong background in HDL coding, verification and toplevel integration $ x1 V5 C" r" K% i
- good understanding of communication interfaces used in Automotive (SPI, CAN, LIN, Flexray) " I7 I% U n. b6 P) z% \+ q
- experience in FPGA development ! h, g/ x1 \8 c# y3 Z
- very good communication skills (written, oral) ; Q! U* O" [% B( a7 Y R% ]- self motivated and high level of flexibility + J+ g1 K+ W8 ]4 t9 Z9 V- foreign languages: English, German (not a must)作者: sophiew 時間: 2014-4-9 02:29 PM
数字IC验证工程师 2 ^7 d0 D5 a) @2 { { ~" @ t& N公 司：A famous IC company& C5 ^( u8 K2 B/ N
工作地点：上海 , K* r2 i# O" H9 l6 r " c8 {: p9 d6 J岗位职责： * t. H/ y' T. ^3 o' M5 M6 x5 o
1、负责整个团队验证平台的搭建、维护 , q( m, j$ K: t a6 J2、先进验证方法和验证平台的评估、导入 ) a6 M$ Q! T6 j: o3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。 3 I" M% k! v" ~- R4 K6 u
( b0 v! a4 Y) @9 t: f/ J3 G
职位要求： # d, }0 o. p( g5 b1、大学本科及以上学历，电子、通信、计算机或微电子专业； ; O8 y$ v( ]/ I) b6 i2 i8 R9 H
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础； - w m$ p, }+ C g) s
3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等； 0 {4 g& y# G( x% Q5 F* E5 n3、有1~2年芯片验证的相关工作经验； 1 y0 m4 @1 O+ ~1 @0 y: p7 ]4、具有较强的学习能力、沟通能力和良好的团队合作精神； * i% ]' M" R V! |% M5、有基于ARM处理器的SOC芯片验证经验者优先考虑。作者: ranica 時間: 2014-4-28 11:07 AM
ASIC Verification Engineer (WMAC) # u8 k( A( q; H6 K* n公 司：A famous IC company q( [; b" x9 U& D工作地点：上海! y s4 V1 w: O2 n7 F
, x4 a& X* Z- rThe Role: " I* ?5 N& l" R! h- s
ASIC design and verification * J* m' x1 K! J% L3 k Work closely with the California teams ( t, t+ i; o6 |2 F* G u0 Q% A Support chip tape out and bring up ) C' P& V; c3 @2 ?, J. Z, I7 D2 i. u6 \, a1 t2 g$ A7 a5 k
Requirement: ) a9 r: d W$ e; {5 \! W 8-10 yrs. experience : w; Z6 N+ ]% g. R9 w: E8 z Knowledge of Verilog / System Verilog & Perl ' D% l! l* @! ?3 v+ w% y1 V Has worked on complex project; experience with 802.11 is preferable i! \- {& Y0 _, B) D$ l+ {& `
Can work independently - want him to take over MVE / G2 W k1 n/ I$ P/ A
Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus作者: ranica 時間: 2014-5-14 02:02 PM
ASIC Digital Verification Engineer , {$ Y! i0 _$ w# s公 司：A mobile chipset semiconductor company/ P7 P1 Q- Q8 }. `4 X
工作地点：上海# V' M9 d, O9 N- _0 v& a/ X
. ]: [8 U+ |% e) t6 j+ ZResponsibilities: ) I0 H+ h$ R: S! T; x9 ~ Make verification plan for one module or whole chip. + h) N- c1 }+ C' w o Build up and maintain module-level and chip-level verification environment A- L, o D3 q; r% u
Verify ASIC digital design based on case list, and output verification report. " _: b% E! U N5 P! C7 y/ D Also responsible for lint checking and formal verification. % m$ [# R, `3 U0 e1 k : a+ w* g( s( s. [Qualifications: : `. Z0 u& q8 N, k$ c9 d* t/ m Proficiency in logic verification. 4 x. s, e2 y4 s, S c" _
Experience with Verilog logic design language. 5 W& B# ^/ r: u+ r
Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language. : c9 _0 N: Z1 U9 }$ k) O" i
Experience with UNIX/Linux simulation tools such as IUS or VCS. ' E9 j* h) h- y }5 C$ i$ j7 s Experience with C and C++ is a plus. . ^8 ~. v; F S1 ]) Y# D
Experience with C_SHELL, TCL or PERL is a plus. $ J! Q, x9 [ D. t Experience with UVM, OVM or VMM is a plus. 7 ^5 L: E% h% v0 u+ u. t, f Good knowledge of SOC design is a plus. 7 `. s; T) d0 S+ ]# [ Good knowledge of software design is a plus. + v6 X$ o3 P& Y/ ~" y; e8 G Self-motivated and good team player. & Z: S! s8 X% p1 A/ g4 b MSEE or BSEE with 2+ years.作者: ranica 時間: 2014-5-30 11:33 AM
Staff Verification Engineer8 O- m# n+ P2 Z/ J7 c- a6 {
公 司：one famous IC company5 Z* \( |% M' R0 I5 L+ K
工作地点：上海# q/ a w3 r% M- B# \8 h& D8 I
/ V4 b& r4 d2 a* NQualifications * q+ x% B+ I! e- A4 A% j# e; WMS in EE/CS/ME. 6 j; V6 w" b1 s( r3 `4 E! d! B1 G# YMinimum of five years experience. . r d8 ^. C( V& u l, M) Y) e
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills. 9 L9 h/ w& o+ y$ K/ g' mCandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology. # n6 Q( j% i. k+ \- ?$ k
Candidate should be familiar with industry standard ASIC design and verification tools and flow. - J J. i( c! }$ x4 U
Good knowledge ddr protocol and computer system achitecture would be an added advantage. 2 ]: |7 \" N4 f2 A, {4 f( aGood knowledge of Perl and shell programming would be an added advantage. * ]* R5 y; a" g- r' k/ L q7 \3 ~/ D: F" |1 }$ K, lResponsibilities: 5 ^& P! A* ?7 p" c
-Understanding the expected functionality of designs. 2 Q q1 M i% M* c8 o
-Developing testing and regression plans. ; B. Q. U' `7 \! h m3 ^( T
-Designing and developing verification environment. " t4 k% L* b- e. H0 w2 }- E. S7 |
-Running RTL and gate-level simulations/regression. % k# g$ c; W0 B6 E3 a ^-Code/functional coverage development, analysis and closure. 5 ]- E9 }0 \/ W" T3 F8 N' V/ r 1 r2 {" J# K/ g3 ^ sRequirements: + Z" l! f& A9 G% v3 [4 p0 S6 V+ w
Experience & Skill: 5 Years ( a6 ^6 v: a" j7 M
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.). ' T, o! M. l7 \4 ~6 m
-Knowledge in ASIC/FPGA design process and verification tools. 0 M" `! M7 z8 s/ G-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.). - N! n$ n; O5 [+ O, M9 b/ k$ D1 e. X& ~" ?
- Scripting and automation skills (tcl, perl, makefile etc) a plus. 9 k! ^$ T1 T: w* o; I6 c-Familiar with C/C++. 1 F2 T# e! F7 @, n) D# l-Knowledge of DDR protocol a plus. & ~" }4 M y* S2 I6 R
-Independent and self-managing.作者: ranica 時間: 2014-6-20 08:56 AM
Staff Verification Engineer . G: O" E/ v$ y; q) p& x! _. i5 }( c 8 l4 f7 T, T5 ?+ U公 司：one famous IC company% j( q0 f1 ]) {8 [
工作地点：上海 9 [4 g8 s+ P, U * b4 J8 F1 z, E& a8 k1 ~Qualifications - C% @* t: Z7 V& z
MS in EE/CS/ME. 9 S6 M/ b) S3 A8 k3 @1 i) KMinimum of five years experience. ; H2 `6 d* ^$ ^Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills. ( e' u+ f# d& y, p7 Z! BCandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology. 7 E4 u, @; L. [Candidate should be familiar with industry standard ASIC design and verification tools and flow. 4 G' W7 q0 q8 h& P2 h+ J
Good knowledge ddr protocol and computer system achitecture would be an added advantage. ; I0 Q* y# Q1 ^: B# k- k
Good knowledge of Perl and shell programming would be an added advantage. * r$ R# ^& w# T7 D3 l/ h% Z
9 |; `0 x6 r' s8 f h+ [Responsibilities: " V* V: W: h) x* [-Understanding the expected functionality of designs. ( o" S6 D1 f, h* K$ S
-Developing testing and regression plans. ! F6 Q7 ^7 K1 \% l! e
-Designing and developing verification environment. " }5 e8 a1 M G6 F% K9 R5 l7 H-Running RTL and gate-level simulations/regression. , V5 J7 Q$ e8 d F, Q-Code/functional coverage development, analysis and closure. * f, G5 n- |" p) K$ G$ Q7 |/ J6 B( C' m! h" I, Q' O _
Requirements: 3 E2 s, m3 N* g/ R" o7 @Experience & Skill: 5 Years 7 ^+ S8 ?$ ^) S-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.). 0 t& t l$ s& e' V3 x-Knowledge in ASIC/FPGA design process and verification tools. : v# Q& Y, s- x0 H$ V1 U
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.). 4 x+ s2 `3 ?0 i7 ~1 r( B; p
- Scripting and automation skills (tcl, perl, makefile etc) a plus. " _$ I Y5 T) N1 p
-Familiar with C/C++. ! h2 y3 J( b+ r9 q/ e7 e3 ?-Knowledge of DDR protocol a plus. " ? _' G7 o2 c0 ]$ J
-Independent and self-managing.作者: ranica 時間: 2014-7-11 10:31 AM
Digital Design Engineer, b; C# U+ h! S# O( c% A
4 w# d" C, `4 m公 司：A famous IC company . D# `" B" m8 K+ c7 F3 Q2 s. |) z工作地点：上海/ d, v% h W3 f
( T) h+ d- Y: J5 i5 l1 e7 p
Duties 4 ?5 G9 k' [. {# a+ n
Work with internal and external customers to understand product requirements. & l# W7 H0 f dCreate critical silicon technologies to meet the product requirements. 9 d! p+ v& g* Y$ u
Work out critical design flows and methodologies to execute implementation flawlessly. _+ t2 x1 f( c" ~8 _( z' X6 r
Design and deliver final design through multiple stages like specification, micro-architecture, IP development, RTL coding, verification, logic synthesis, DFT, timing convergence, as well as helping on physical implementation.* L) x5 }2 t2 q/ n' y
Complete full documentation. / ]! l' `/ _5 O! f' a
Help and mentor junior engineers. ( A) r7 k1 o8 p- Z ) z9 Y9 W) [4 N1 ?1 R0 h: t. t. R% oJob Requirements: 9 y; y' M/ t* d: q0 l; d! o$ t
Solid understanding of all SoC chip development stages is required. % I" A3 E; h. w6 p) MHands-on Experience with complex SoC design flow is required. : x7 H9 A& L& F& {" T4 U6 T0 n
Hands-on Experience with RTL coding, simulation, verification is required. ( P/ n5 O" M) L4 V* ^& a
Experience with DFT and timing tools is preferred. 8 _; V* h$ _0 m* wExperience with ARM platform is preferred. ) m. b! [* ?/ j' k7 x3 D& r4 ~Experience with low power design flow is preferred. 9 i4 u. N# U1 e% ^8 n! ]+ j& bExperience with system verilog is preferred. * y, Q' a" f3 j8 b& c" HGood organization and documentation abilities ; ?" l9 U: E( @/ i0 U+ cMS in Electrical Engineering and Computer Science with 4 years of experience in SoC design作者: Ali-pig 時間: 2016-9-9 08:00 AM
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