Theme: Energy and Variability Aware Circuits and Systems
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The continuous scaling of devices technology has introduced drastic variation of process and design parameters, which lead to severe variability of chip performance in nanometer regime. As uncertainties due to process and technology variations are expected to increase in each generation, it will have a significant impact on the chip performance as well as the reliability and yield. Another challenging issue is the high power consumption due to excessive leakage power and higher packing density in nanometer integrated circuit and system design.
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As a result, circuits and systems are often over-designed to compensate for these uncertainties and variations. These over-designed circuits and systems not only will increase chip area and power consumption but also make timing closure, matching and optimization difficult. All these technical challenges will inevitably reduce battery life in portable applications and impose greater challenges in cooling and packaging in non-portable systems. $ |+ S# j2 `/ ?; M* F
This Chip Design Competition aims to address some of these complex issues, improve the chip design productivity and develop new design methodologies, novel circuits and systems to circumvent variations in process technology and power/energy.
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Prizes and Certificates:1 R9 f/ _( ]& D+ ?9 e1 s$ Y
A total of 10 cash prizes will be awarded, which comprises: 1 C2 [6 q }8 e% T1 V5 O
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/ Z7 `2 j9 P! ~One gold winner S$10,000 Two silver winners S$6,000 each Seven bronze winners S$3,000 each |
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