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標題: 11/19-20 Semiconductor Manufacturing Forum 2009 [打印本頁]
作者: chip123    時間: 2009-10-21 05:58 PM
標題: 11/19-20 Semiconductor Manufacturing Forum 2009
由台灣半導體產業協會主辦之「2009半導體製造技術論壇Semiconductor Manufacturing Forum 2009」將於11/19-20於新竹交通大學舉行，會中邀請關於Thin Film、Asembly, Packaging & Testing、Diffusion、Design, Reliability & Testing、Litho與Etching等專家對未來趨勢與新技術進行專題演講，是半導體專業人士不可錯過的一場盛會，即日起開始報名，歡迎各界踴躍參加。+ a+ [) W/ \+ {5 A) a
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2009/11/19-20 National Chiao Tung University Library International Conference Hall
0 @: i1 [! A4 _9 H1 o交通大學浩然國際會議廳
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( S* A0 Y) d# ^Agenda 議程
0 I2 t" D. f, M( x7 U2 g' s  d# kSession 1: Thin Film (11/19 13:20-16:20) # w3 f3 I7 V0 N- {, a9 H
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Topic
Speaker
13:20-14:00) u, j  Q% I. a
Engineering Slurry for Copper Chemical Mechanical Polishing 6 d2 e0 j7 L# g. a/ h: _* n
Dr. Song-Yuan Chang /
/ J) x- O5 U% h/ B, @1 ]& m* `CTO& senior VP, UWiZ2 [) S" S9 p; |; a3 u- ~6 ~( @
Technology
14:00-14:40
$ p* \. G% {+ R( o* ?' d		Tailoring CMP Consumable Sets To Meet the Increasing Demands Of IC Device Manufacturing For Advanced NodesDr. Fred Sun / Cabot' d+ b" i; s+ _( \
14:40-15:00' n+ K% v) k% ]) W( J2 E$ r* I* N% g
Break
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15:00-15:40
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Apllied Materials% j1 c6 i' H& D" f
15:40-16:20; j8 W  k. K, t6 r: `1 X
CMP Fundamentals and Implications for Consumables Design
( T6 j+ v4 ?' g; j$ I( H6 p		Ms. Kate Kao/ Marketing Manager Dow chemical
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線上報名：http://www.tsia.org.tw/activity/events_more.asp?qwy+0AqiqcNKmMZ
作者: chip123    時間: 2009-10-21 05:59 PM
Session 2: Assembly, Packaging & Testing (11/19 13:20-16:20)
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2 H7 S5 `( {1 L* A2 ^1 S3 H		Topic
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13:20-14:00
" s" @- c. m5 n% A" P0 c  d		Sip Assembly technology?0 s7 e; J; k) |4 ]8 l: W6 g
Dr. KC Yee/ VP, ASE
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14:00-14:40; N( i( b/ \9 m3 X) M" ?+ P
Assembly trend from perspective7 p& b9 i* _* `$ M3 \. I0 H
邱世冠 資深經理/矽品
6 @2 M" B) ~5 A2 j5 H前瞻科技中心, d& G+ p* G5 l* z0 s. u
14:40-15:00
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15:00-15:40: O% |# b0 a/ a0 d; a! R( S; c
The Paradise of Cost-Effective Wafer Probing Technology6 y2 z) V6 ^* I, i
Dr. CCNi / Associate Director , KYEC9 u! e1 J( |4 S5 z$ S" v- {3 `: I
15:40-16:20
5 G- h/ I" Q4 q0 U		RF SOC /Sip?. ]8 \: m: W! p$ f
Verigy# g2 E: W3 w4 @- {  p. d' H
線上報名http://www.tsia.org.tw/activity/events_more.asp?qwy+0AqiqcNKmMd
作者: chip123    時間: 2009-10-21 05:59 PM
Session 3: Design, Reliability & Testing2 t9 t7 s+ w3 L

4 v3 b" }0 P! j2 o1 f/ h" U		Topic7 u, r3 p% `3 \# I& U( y' z' w" g
Speaker
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9:00-9:40
3 _4 s* A2 s0 L7 f		Design Trend?5 M1 M8 L& g- J
Marketing VP, Dr. Chiang Alchip
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9:40-10:20$ \7 k' x' \. n8 O
Charged-Device-Model (CDM) ESD Protection in CMOS Integrated Circuits / ]3 t1 W8 A% ~
Prof. Ming-Dou Ker / I-Shou Universit   - S: p' K. F8 j, O" M9 {1 B. V
10:20-10:40
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10:40-11:20# o! }  X# |! I& e9 W; C: j) T% o
Parametric Test Challenges of the Next Process Frontier
; a# j. M: r: C+ D- f		Ms. Flory Tsai / agilent
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11:20-12:00
: i' o# J& T* ?3 _* h6 f, l		Recent Development Work and Trend for Semiconductor Device Characterization
% d  e7 s0 W5 {. k5 b		AL Feng / 專案經理 / Keithley Taiwan
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線上報名 http://www.tsia.org.tw/activity/events_more.asp?qwy+0AqiqcNKmMh
作者: chip123    時間: 2009-10-21 06:01 PM
Session 4: Diffusion
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" D+ f7 b" F) w		Topic: l0 r5 q6 p9 G) b, z& Y0 ?( s' R
Speaker, P7 _3 F% p& _1 g/ S. }
9:00-9:40
4 g% ]: @: t2 H$ x		Surface Preparation process control requirement to support CMOS scaling into 22nm
. U  _% f5 R0 I6 l		Dr. Scott Becker/ Vice President, FSI9 l/ ?3 {/ m  V! v7 ], D
9:40-10:20
% `: a* {% m* F) U) V		Wafer techincal roadmap and application for advanced or special proces
* a  e1 p7 A8 G7 F( [5 _		MEMC
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10:20-10:409 F( j. Y* P+ L  s3 C$ a# O
Break4 H( M7 x7 @6 K# j5 n& N4 k* w
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10:40-11:20$ a1 Q) w" F5 F% _

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線上報名：http://www.tsia.org.tw/activity/events_more.asp?qwy+0AqiqcNKmMl
作者: chip123    時間: 2009-10-21 06:02 PM
Session 5: Litho2 E1 M  ]' ?) w& c" G& k& d
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Topic$ g1 K/ }# o% W2 Q1 ]+ o. c. |+ P
Speaker  m4 S3 o* S5 i  C, |2 b; {
13:20-14:00
  a0 [6 X6 H  e9 n/ H5 T		Photomask technology for 32/22nm and beyond6 f7 r6 D; J; S$ A
Dr. Hiroaki Morimoto/Senior General Manager,6 q. C( H: }2 ]4 x: z8 ?: J
Toppan Printing
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14:00-14:40
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# x8 M: V. D+ G# A( UImplant Resists for Advanced Node Applications+ B3 y+ q& C% K' h" w
Mr. Yoshiro Yamamoto/ 5 y5 l. w$ ]' Z) v( j0 D* c8 ]& ^
DUV RD mamager, DOW2 M- Y) ^) D# O
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Semiconductor Technology ) K" B, L. G: ?4 m& e
14:40-15:00
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15:00-15:40
! n% @/ M5 C% |" a4 i; W		State-Of-The-Art Development of BARC Material
6 k" a1 v  i( f: J		Brewer Science
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15:40-16:20
  X  j+ r6 q5 d3 j% h		The Future Trend for Next Generation Lithography
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16:20-17:002 B- v- ?+ W% J/ D) s5 j
Future Trend of Track Technology
( h3 _( N: D3 C  R: h* b  v$ y1 D7 m		TEL. T( N$ I/ Y" R/ _6 V: O
線上報名 http://www.tsia.org.tw/activity/events_more.asp?qwy+0AqiqcNKmMp
作者: chip123    時間: 2009-10-21 06:02 PM
Session 6: Etching) v1 D  A# K0 d- C8 s( t$ F: K
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Topic
- {( s7 i" Z1 X) X9 b6 S		Speaker$ I) V( Y- n- x0 H' }
13:20-14:00
: P+ {- o$ [0 g* X  S! E- W) i5 Y' _		The Advantages of real-time wet process monitoring by multi-channel, in-line NIR analyzer 7 b* ^( b0 t3 `* k) z
Mr. Shay Tina / CI Semi , Director of Sales, V4 a6 Y; `- C: f% U# b
14:00-14:40
7 b6 W3 {9 p$ Z, L: b$ E		Green Chemistry for current technology and beyond# Y) t; q# Y/ w( _+ z( v+ J
Mr. Elvis Sheen / Mallinckrodt Baker, Senior Manager
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14:40-15:00* m1 Y' Y4 K  @4 K% a- R3 W& }
Break
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15:00-15:40
! q$ T; G6 n7 {& x* F+ w& x0 D. V		Post-etch residue removal for advanced copper low-k device
( x7 p- I$ J' J. U# \7 |* d		Dr. Hisashi Takeda / EKC Technology, DuPont
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15:40-16:20" y  z! \, Q8 M$ u0 i! d1 N: Z4 Q
Edge Die Yield Improvement with Immersion Lithography Defectivity Control by Bevel Etch Clean; L' R" t$ r  L% V% u
Lam Research8 }4 T4 C" r- w( ?* p
16:20-17:00
* z  U1 W& z) S7 b9 I5 \, c  ~: }		Improved Control of Through-Silicon Via Profiles for Advanced Packaging Applications5 B; }3 Y; f2 j+ I' t# e
Surface Technology Systems
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線上報名http://www.tsia.org.tw/activity/events_more.asp?qwy+0AqiqcNKm89



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