標題: library compiler建DFF cell的疑問 [打印本頁] 作者: 霜淇淋 時間: 2009-9-17 02:02 AM 標題: library compiler建DFF cell的疑問 各位好,小弟打算跑HSPICE改變一下cell library的資料- t2 L/ T$ V1 K8 I
但有部分還是不太理解,以下是D-Flip Flop(DFF)接腳D及CLK部分 f$ [5 W! b2 e E6 t w2 p1 k& h: @! Q2 u& `' b
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pin(D) { 5 R3 @! y; k3 v% V! I2 T( c nextstate_type : data; 2 h. A# Z! K+ ^ direction : input ; : y& W! i: U- e S$ ? capacitance : 0.001165;" ~" D! ` Z/ B, u* @
internal_power() {( T3 j( C0 V& S% h, o. V- V, P
when : "!CK"; ! Y) r; {7 X t( i* Q5 k power(POWER_7x1) { , F( Z7 j+ k$ Q9 `) F6 J- q: s index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");9 y* A4 ] C6 Y' N, i% [3 i" b
values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");2 m6 c0 H8 B+ I7 ?$ ?: @
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values值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎? * j! |2 n7 ?0 X" `, s) O7 \1 F( B 4 l) l+ j# w5 d$ U& X, [; [& A$ d" } internal_power() {$ _* {1 l+ r2 z4 N2 W U) r
when : "CK"; - m& [8 K6 `1 D+ z6 ]! y/ P5 z power(POWER_7x1) { + ~* G- s3 r3 ^0 H V9 O n& J- l$ r index_1("0.009645,0.016106,0.025991,0.046674,0.088957,0.216628,0.447814");1 x1 t3 D- G& u$ N
values("0.000127,0.000122,0.000120,0.000119,0.000117,0.000116,0.000114"); 4 B8 V$ o# o, H2 v. Z Y3 U }7 z" o. B' O9 y. }0 ]
} ( q# J2 x% u2 m8 s timing() { " Z0 U, A$ ? f* e# u related_pin : "CK"; 6 r' p3 G/ i8 V* z7 E1 ^ sdf_edges : both_edges; , {; j! i1 j$ O- ^$ W, W* ]9 O1 V timing_type : setup_rising;/ M" ~: {5 s8 _- z+ S
rise_constraint(CONST_3x3) { 0 b) D7 I3 S: P, X9 v! |/ r0 X index_1("0.006000,0.217000,0.434000");: S4 D, Y* H8 j6 Q
index_2("0.006000,0.108000,0.217000");1 ^+ _8 U; V: A; i4 t
values("0.029659,0.026470,0.036963",\8 x# a* C# c* h! M# W. v) n5 ~( t
"0.032032,0.023912,0.031939",\ , ^* x' o% c$ Y) p "0.004917,0.000010,0.004825"); 2 |' ]% o2 v- B- @ }5 K7 _6 Y5 J5 N) w" ^/ A8 t5 p+ C
& d' A# E# v, u, D) w/ l2 Uvalues是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎?% X% b( L6 p6 W5 ]
$ K9 n/ P* X7 A2 Z6 a" X " t+ G, |! `, m0 x7 L( x4 e fall_constraint(CONST_3x3) { ; [' s( a1 m- ?2 b4 | index_1("0.006000,0.217000,0.434000"); , Q+ g0 j! B2 w7 b, l" e/ b index_2("0.006000,0.108000,0.217000"); b1 |4 W3 I( A& H values("0.074043,0.058526,0.059156",\6 _$ t r8 J- c/ w6 [" K
"0.152860,0.139810,0.137970",\ 4 {# X. C: U* C. n "0.231770,0.216260,0.216890"); / u8 b) K$ |( F% {# F( z2 ^! m4 ? }9 V, ]' J, X) q5 ]2 }) T
}作者: 霜淇淋 時間: 2009-9-17 02:02 AM
timing() { 6 v& X3 X7 c" ~& C# e2 V; H L+ o related_pin : "CK"; 7 Q$ c* _% V1 V sdf_edges : both_edges;( t' y" \- B6 R
timing_type : hold_rising;8 K$ }) N9 d0 [' f+ @" V
rise_constraint(CONST_3x3) {& g8 r4 C2 `8 X4 p; H' |
index_1("0.006000,0.217000,0.434000");9 w* D5 x$ i3 j) O$ [( s7 T
index_2("0.006000,0.108000,0.217000");( `1 p& a+ A8 Z% @* S5 V$ O
values("-0.005932,-0.005209,-0.015703",\, U- Y% J. I/ [* x- n0 W
"0.013887,0.014610,0.004117",\ $ g9 B. T) F3 h" p "0.060728,0.056519,0.043560");* z2 [( m/ r( z! \* N" ?" n6 L8 S
} 7 I( a3 ~# R8 W9 s9 z! C n fall_constraint(CONST_3x3) { 0 Z+ o% i0 @% `9 J0 y index_1("0.006000,0.217000,0.434000"); 6 ~* D c9 X2 l8 q# Z index_2("0.006000,0.108000,0.217000"); ; Q2 F8 S9 H+ j( _ values("-0.018261,-0.002744,-0.005839",\; h+ T$ u/ M# o2 m# {* [
"-0.028829,-0.021521,-0.028745",\0 \) U" k Z g" H
"-0.004426,0.053203,-0.004342"); 4 N- T* o8 _3 |9 J! N" S- F }' W/ _5 z4 {! t) l0 ]; _4 E& t0 L+ g# k
} ( { C+ g9 x+ O' D4 I } ' [. P* \2 d. o: j pin(CK) { ; M' v7 y, g, m1 p. n' s, ? h direction : input ;2 j: D; P) E! F$ P# ]
capacitance : 0.001915;- U; k& B1 y% X* c, O# ~
max_transition : 0.217000; ( v# w$ D" }. b& {5 f# n' d0 b clock : true; 3 X! {( O6 V6 [/ d$ L) { internal_power() { 8 }! B% N3 o8 D power(POWER_7x1) { 9 {2 M3 _& c" }% ^4 L index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");" p' d% S0 c# Q
values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062"); 1 R+ ^( y$ ~4 G8 j1 J3 d, | }. b0 R ?) J- \& U; n0 y
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A2 i2 R4 _& U$ l f+ v$ ]values值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎? : U, o8 Q, P, ]8 W0 W$ E7 d- H. @9 A: A
min_pulse_width_high : 0.061268; 4 \. I* M/ g( q2 p4 L min_pulse_width_low : 0.125320;0 |7 z5 B, w& n
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CLK Hi/Low的長度?# t( S# c# _; _* M- P! ^
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有觀念誤解的話希望幫忙修正..謝謝 a4 u d$ \* ]' n" b# _
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[ 本帖最後由 霜淇淋 於 2009-9-17 02:03 AM 編輯 ]作者: yytseng 時間: 2009-9-28 09:40 PM
internal_power() {3 q5 }- k% v8 D5 F0 n8 a0 t r$ x
power(POWER_7x1) {+ |9 b3 I: Y# A# ~
index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");% u; ^2 y8 T# n4 y; x5 x
values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062"); : a8 S4 o6 z) |) C/ o/ ]$ ]/ Nvalues值是指不同的CLK端電容(index_1)在CLK=0時的POWER值嗎? . W4 X \1 z5 `! c% t===> Wrong ! + ?) u* e k2 g5 k+ e4 E( n===> they mean while different input slew (transition) of CK, results different internal power 8 y) R8 M2 e3 u$ a$ a) g$ Q/ h. v: p+ d) t. L
min_pulse_width_high : 0.061268; : r$ ^7 g) ] n9 V% D; T6 Umin_pulse_width_low : 0.125320;5 [1 c: F/ t7 W
CLK Hi/Low的長度? 2 l8 L' I% r7 B) P* _====> No, these mean minimum possible of clock waveform to prevent functional fail, for high (1) and low (0)# ? h# s, o) C1 [3 u: R
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index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814"); 9 @+ q7 \' ?) L values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117"); # V6 u, G. {! J! I& k }3 b& n# u7 E! u3 }( i" f8 M
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* y# c. J$ h( u4 b* Gvalues值是指不同的D端電容(index_1)在CLK=0時的POWER值嗎?4 u- K$ b) G; m" M& Z0 J/ J
==> No, index1 is often input transition. here represents input slew of D pin 1 P# f; U8 X% j) x* A& h( t% | 3 \( h0 O' h% f: ^ index_1("0.006000,0.217000,0.434000"); 4 M. ^, }9 C+ ]5 E. t& C% E index_2("0.006000,0.108000,0.217000");7 [* E M- L9 @; y) l
values("0.029659,0.026470,0.036963",\ * Y2 b O- P- m! S* [3 v "0.032032,0.023912,0.031939",\ 2 Q' v" a" n3 ]$ Q6 r7 b "0.004917,0.000010,0.004825");1 r9 m# ~) F3 U
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values是指DATA輸入transition time(index_1)跟CLK輸入transition time(index_2)不同時所得到的setup timing嗎? - |! h2 {+ Z/ m4 b 9 O7 E" x: I% ]: t4 e C===> yes, but you have to refer index_2 definition in the front of liberty file to make sure.