標題: 關於電阻的設計 [打印本頁] 作者: squirrel316 時間: 2009-5-22 12:17 PM 標題: 關於電阻的設計 在CMOS製程中 / ?, ^; a! z5 X _% v大致上可以知道說阻值等於sheet resistance*(L/W)7 n" O% p4 N$ ~8 d$ s
不過我有個問題就是L跟W值的選取 + ?# s0 Y& W! D1 g' f4 @6 G假設我要讓L/W=2 ( J* v, \8 x4 v! C, P我可以有很多種選擇 像是2u/1u 4u/2u ...等0 h$ ~( P* c. \8 n! o) a
那請問一下這幾種選擇除了雜散電容造成的影響之外. ^+ \& V# S2 u: u& s& m1 `
還會有什麼影響 v8 U. x) [6 W q3 H x謝謝指教作者: seanyang1337 時間: 2009-5-22 03:30 PM
Dear squirrel316, 8 D7 D3 s3 b4 W" cBasicly, the W should big enought and has a low bond(usually 2u for above 0.35um).% w2 A6 C* `7 r& d6 g
If you using too small scale like 1um, the accuracy will be very poor.: l: e9 {8 ^ `6 \/ Q* K- `
And it should be considered the eatch value.9 B+ p t8 b/ s. k1 s' ~$ }
As a reference, the foundry resistor test key, was measured by 10u/10u or larger.