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標題: verilog 觸發的問題 [打印本頁]

作者: scroll529    時間: 2009-3-26 07:44 PM
標題: verilog 觸發的問題
請問...." u* m# p7 o- S
    always (*)
8 ?% r" p$ j( j; }, j     begin% x9 P7 h1 ^5 g+ F/ g
      if(!rstn) r1 = r2 + r3 ;3 c8 D* S; \, K( m" {; A% o
      else      r1 = r5 << 4;
. f) X: x' F% {3 t% G     end* d+ p5 j4 d9 C2 c0 D4 r
    請問*是表示r2.r3.r5的意思嗎,如果是像這樣子的寫法是否能夠合成' S! _( G' ]2 M- ~
   ! a2 V* ]! G4 }7 N, I7 V
     小弟才疏學淺...謝謝各位大大
作者: newwalkman    時間: 2009-3-31 07:57 PM
敏感表中不仅是要传送的值(r2,r3,r5),还包括判断条件(rstn)
作者: spring69393    時間: 2009-4-4 08:50 AM
敏感列是只要那個變數有變化,就重新判斷一次, * 應該是沒有效果才對,5 K9 k) a/ }  [% E9 V0 r! r- {
你這樣寫法應該會造成出來的值是跟你所要的不同結果。
作者: videochip    時間: 2009-4-17 06:46 PM
可以合成 !!
* ^4 i: _& ?1 }! W( C不過應該是這樣吧$ `+ o. S& x! ?5 q2 k. A

% P+ w) Q0 e5 \& d( Calways @(*)
, y- p9 [  \4 U# `$ f2 Q     begin
; `( |9 @2 k6 Y* t# q8 Q8 Y      if(!rstn) r1 = r2 + r3 ;( |6 j, s9 Z8 F) C3 r
      else      r1 = r5 << 4;
" m1 D7 q5 O3 A1 p9 e     end
作者: masonchung    時間: 2009-4-22 06:30 PM
這個是 verilog 2001 的語法喔
作者: 賈斯丁    時間: 2009-4-28 12:44 PM
Verilog-2001 added the much acclaimed @* combinational sensitivity list. The primary intent of this enhancement! t7 s3 T/ E; B# s1 g! _2 v8 a
was to create concise, error-free combinational always blocks. The @* basically means, "if Synopsys DC wants the6 K) _8 _5 h6 p: U1 _" h3 u
combinational signal in the sensitivity list, so do we!"
5 e; q2 o% F% g3 {8 U1 A% i/ gExample 1 and Example 2 show the Verilog-1995 and Verilog-2001 versions respectively of combinational
: s( z: f- ]* c2 `1 {" m( J0 bsensitivity lists for the combinational always block of any of the three always block fsm1 coding styles.
7 Z! S" V# ?- y& b; Z) T5 P
- G# v9 q$ ^( G3 c, i* w0 Ualways @(state or go or ws)) q& Q5 }) b$ b9 F
begin. \$ T6 {! V2 v" u, G* M% Q
...
9 Z' v: M2 E. cend7 E' h  D5 R, }7 d, N2 @
//Example 10 |/ k/ Q& Y) c% ^& P) Z/ ?

  H7 t' L) ^* p7 W* d
  z" o, V2 C  T, b  W; j$ Walways @*
2 W5 N, P! U2 k. l# n+ T. Y% V& kbegin
. \0 t' q2 ?0 i6 {6 ?+ C" O% }...$ \/ @+ Z$ M% [, ^2 z( t
end
( u$ `) o1 t3 \7 N4 T" K6 S4 e//Example 29 H" h2 d7 E& G6 I( v3 a

% C  D8 q: }. Y* w# I4 r; l6 o6 {The @* combinational sensitivity list as defined in the IEEE Verilog-2001 Standard can be written with or without
) X4 w1 `) K5 t& rparentheses and with or without spaces as shown in Example 3. Unfortunately (* is the token that is used to open
7 p7 \# v8 J! P. o) ea Verilog-2001 attribute, so there is some debate about removing support for all but the always @* form of this
4 R/ a7 o' X; xcombinational sensitivity list. In-house tools would probably also be easier to write if the in-house tools did not
3 m: h. A5 h+ I" V6 [3 i; R. Q: }( jhave to parse anything but the most concise @* form. For these reasons, I recommend that users restrict their usage
) x( x& Y3 t4 d9 x$ v; aof the combinational sensitivity list to the @* form.* @$ d" {/ o/ p6 S0 i* N$ s' V
always @*
; R6 z% C5 F- @: z* v& B/ U6 Aalways @ *0 }; [% B$ b; T# ]
always @(*). f  F/ I; Y% u4 \: Q4 f. k. M) s" g
always @ ( * )
1 ~7 y+ M+ @% x: v. ^3 |9 E//Example 3




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