標題: 1/21 交通大學Multi-Layer Stacking Technology and Trial Manufacture研討會 [打印本頁] 作者: chip123 時間: 2008-1-18 02:03 PM 標題: 1/21 交通大學Multi-Layer Stacking Technology and Trial Manufacture研討會 在半導體製造技術趨勢往大尺寸晶片與微小化元件發展的同時，具備元件高整合度解決方案的系統級封裝(SiP)技術的快速崛起，更受到半導體晶圓代工與封測業者的高度重視。SiP技術發展中，晶片或裸晶的堆疊技術(3D stacked IC technology)更是未來注目的焦點。
此技術研討會邀請到在晶片堆疊技術領域有卓越成就的日本Honda Research Institute Japan Co.,Ltd.研究團隊Director Nobuaki Miyakawa(宮川宣明)發表3層8吋晶片的堆疊技術，該項技術已成功在8吋晶圓廠內將3片不同電路的晶片，透過目前備受矚目的新興連接技術矽穿孔(Silicon Through-via)與晶圓黏合(Wafer Bonding)，來達到晶片的堆疊與各層晶片間的互連，並且完成相關電性與良率測試。運用該項技術可以快速將不同系統功能的晶片進行垂直整合，達到短小輕薄與降低封裝成本的需求。另外，透過晶片間的垂直互連，可以降低高整合度系統晶片的功率消耗與提昇運算速度。未來將是另一個重要的半導體技術發展方向。
(研討會全程以英文講述)
Outline :
1. Process flow of new wafer-to wafer stacking technology
2. TSV Structure and Electrical Connectivity between TSV and bump
3. Test results of trial manufacture based on 8-inch wafer
4. Design methodology of trial manufacture
Abstracts :
We have developed the new 3-dimentional stacking technology and made the prototype device by using wafer-to wafer stacking method. Each wafer is fabricated by using 0.18 μm CMOS technology based on 8-inch wafers. The electrical conductivity between each wafer was almost 100% and contact resistance is less than 0.7Ω between a thorough silicon via (TSV) and a micro-bump. We have also created a prototype of a 3-layer stacking device using our technology. The performance of trial devices showed two times better than that of MCM device case using 2-dimentional device with quite same functions through the power consumption is almost same. The yield gotten from the results comprising all functional tests are over 60%.