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標題: design through verilog HDL [打印本頁]
作者: jearome    時間: 2008-1-17 05:23 PM
標題: design through verilog HDL
Design though verilog HDL7 y6 j. W5 [% N9 V7 V2 b2 i. M
T.R.Padmanabhan. J- e6 t: I/ I6 I9 N" ~* X
B.Bala Tripura Sundari
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" M( p7 n/ {7 y+ C. W* sa very nice book![local]1[/local]
作者: cmyang    時間: 2008-1-21 09:20 AM
我好想要看看, 不知要如何得到呢?



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