標題: What Custom IC Design Challenges are you facing now? [打印本頁] 作者: jiming 時間: 2007-11-12 05:38 PM 標題: What Custom IC Design Challenges are you facing now? Please select the following issues that you believe EDA Tool Vendors should invest in based on your experience and design needs. :o " X$ E2 c+ r$ }' X3 @' u
- O" V& d- y' t3 ~ Add your comments to further explain how these issues are impacting your design process. And let's discuss these before 2008.. o K0 ~/ x2 t4 h2 }0 q' X
! N9 i9 g* L o6 @1.Time and schedule ; a# E/ E1 R4 m: e/ d9 G( c2.Parallel designs e.g. layout and design engineering working at the same time, ?( ^2 L" Z0 G3 D
3.DRC/LVS/ANT verification 1 ?7 W6 C5 {( O. _4.DFT" ]9 P& j/ o" ^
5.Working in a multi user environment- R8 G1 |9 _5 t/ F9 y. S
6.Incorporating latest process node specifics (e.g. .65, .45 CMOS) . v- T% d. P& m1 y( j. R4 P5 h P
7.More than Moore technologies, such as high voltage design, high frequency design, high current design, high temperature design, multiple - F, @+ H: P$ g" L) R, t technology support in a single design, Mems , H; r4 i# q3 c5 Y0 `/ h8.Incorporating RF blocks into standard designs (RF SoC Design) 4 _- w' N1 z/ m' Z$ ~' y) W' b) {9.Dealing with low-power design constraints in an analog world4 _5 D/ m1 S# L% v
10.Entering, tracking and verifying design intent between electrical and physical design }1 ^8 W9 r# `3 h8 W; r3 N; i2 a6 N
11.Assessing parasitic sensitivities prior to full layout # H( `+ V ^$ E* d6 x6 u, t; Y12.Optimizing circuit construction at 65nm and below $ m3 m9 `; o! L' g6 g2 L
13.Techniques for design centering to achieve optimum performance / yield% ?' j! t) n8 |7 R. f
14.Designing up to to six-sigma yield margins , P! I+ g/ g; i' d- x7 h- i15.Other, please specify:
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