時間 | 活動內容 5 P: d* M' z1 q' y6 l) Y | 主講人 |
1:00-1:30 | Registration | X& ?, Z Z l |
1:30-1:35 | Introduction: Agenda, who's here, what do we do?/ Z" a5 T* C5 e# x. Y* J | |
1:35-2:05 | Key Note: Why prototype?" F+ G2 R1 ~ X K ASIC Verification Options1 T! q4 _1 f3 i L% p | Ashok Kulkarni,Technical Marketing, Synplicity7 V9 t( y0 \) Q1 n" Z6 W |
2:05-2:50 & o" L8 _& Z+ N1 k D* m! @ | V5 for ASIC Prototype | Simon Ho, Corporate Solution marketing Manager, Xilinx7 a$ w& |/ O0 P% { |
2:50-3:10 | Break! R2 g7 u Z9 S4 S: N& p+ \ | |
3:10-3:55 | Creating a platform around you FPGA(s) ( B) T( u, F+ i$ J7 O3 D | Ashok Kulkarni,Technical1 H+ X; N, G8 u$ g" K# @( }+ o Marketing, Synplicity |
3:55-4:25 & E. ?! N) b1 B/ ~/ t& D | Faster FPGA Implementation0 v& g4 T. ^, Y) O7 [1 r* j7 a | Simon Ho, Corporate Solution marketing Manager, Xilinx$ k) p3 {6 F6 k/ L0 C! p |
4:25-5:00 - T4 x, i# `4 u! Z5 b/ o8 M" _ | Making the ASIC design ready for FPGA - HAPS live flow demo | Freddy Lin, ASIC Verification Specialist, Synplicity Taiwan5 ^+ O& i& H) [& [4 v+ d |
5:00-5:30 3 c9 _6 Z& [: U5 B4 p l1 x | Q&A, Lucky Draw and Wrap-up) @$ e% r3 X( r$ R2 I; |6 S | All4 L+ K1 c. g. g9 W& l |
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